Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification: Lack of Proper Antecedent Basis for Claim Terminology
The specification is objected to under 37 CFR 1.75(d)(1) as failing to provide proper antecedent basis for certain terminology appearing in the claims. See MPEP § 608.01(o).
In particular, the specification does not clearly identify the disclosed structure corresponding to the claimed “backside dielectric plug” recited in claims 1, 4, and 10 or the claimed “backside dielectric layer” recited in claims 17 and 18.
The claimed “backside dielectric plug” appears to correspond to a structure including the first liner 232 and the fourth dielectric layer 234 shown in FIGS. 22A and 22B and described in paragraphs [0038]–[0040] and [0047]. However, the specification does not identify the first liner 232 and the fourth dielectric layer 234, either individually or collectively, as a “backside dielectric plug.”
Moreover, claim 4 recites that the backside dielectric plug includes “a bottom dielectric layer spaced apart from the isolation feature and the first epitaxial feature by the first dielectric liner.” This claimed “bottom dielectric layer” appears to correspond to the fourth dielectric layer 234. However, throughout the specification, the term “bottom dielectric layer” is instead used to identify element 204. See, for example, paragraphs [0016], [0018], [0024], [0031], and [0037]–[0043]. Consequently, it is unclear whether the “bottom dielectric layer” recited in claim 4 corresponds to the disclosed bottom dielectric layer 204, the fourth dielectric layer 234, or another dielectric layer.
Further, the claimed “backside dielectric layer” recited in claims 17 and 18 appears to correspond to the fourth dielectric layer 234 shown in FIGS. 9A, 9B, 22A, and 22B. Nevertheless, the specification does not identify the fourth dielectric layer 234 as a “backside dielectric layer” or otherwise expressly establish the correspondence between these terms.
Applicant is required to amend the specification, without introducing new matter, to provide clear support and correspondence for the claimed “backside dielectric plug,” “bottom dielectric layer,” and “backside dielectric layer,” or, alternatively, to amend the claims to employ terminology consistent with the specification.
Specification: Collectively Numbered Figures with Alphabet
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, ‘Figs. 2A-2D’ in the paragraph [0012] and ‘Figs. 4A-4P’ in the paragraph [0012] are objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Appropriate correction is required.
Specification: Informalities and Internal Inconsistencies
The specification is objected to because of the following informalities, typographical errors, and internal inconsistencies. Appropriate correction is required.
• Paragraph [0013] recites “MBC transistors having a plurality of a channel members.” The phrase should be corrected to “MBC transistors having a plurality of channel members.”
• Paragraph [0018] identifies the n-type dopant As as “arsenide.” Because As denotes arsenic, the phrase “arsenide (As)” should be corrected to “arsenic (As).”: Arsenic is a naturally occurring chemical element and metalloid, whereas an arsenide is a specific chemical compound formed when arsenic bonds with a metal.
• Paragraphs [0018], [0019], and [0021] recite “yittrium.” Each occurrence should be corrected to “yttrium.”
• Paragraph [0020] recites “After the top surfaces of the workpiece 200 is planarized.” The subject and verb do not agree. The phrase should be corrected to “After the top surfaces of the workpiece 200 are planarized.”
• Paragraph [0034] lacks a period at the end of the paragraph. Appropriate punctuation should be provided.
• Paragraph [0035] recites that “method 100 includes a block 306.” Because block 306 is part of method 300 shown in FIG. 10, the phrase should be corrected to “method 300 includes a block 306.”
• Paragraph [0038] refers to “recessed drain epitaxial feature 212.” Elsewhere, the drain epitaxial feature is identified by reference numeral 212D. Accordingly, “recessed drain epitaxial feature 212” should apparently be corrected to “recessed drain epitaxial feature 212D.”
• Paragraph [0041] recites “sidewalls of the source contact trench 236 on the X-Z plane is lined by the first liner 232.” The subject and verb do not agree. The phrase should be corrected to “sidewalls of the source contact trench 236 on the X-Z plane are lined by the first liner 232.”
• Paragraph [0043] recites “Operations at block 322 does not remove.” The subject and verb do not agree. The phrase should be corrected to “Operations at block 322 do not remove.”
• Paragraph [0044] recites that the metal precursor “may be in contact with that the isolation feature 203.” The phrase should be corrected to “may be in contact with the isolation feature 203.”
• Paragraph [0045] recites that “top surfaces of the substrate 202, the liner 238 and the backside source contact 242 may be coplanar.” This statement appears to have been copied from the description of the first embodiment and is inconsistent with method 300. Method 300 employs the first liner 232 and the second liner 239, rather than liner 238. Further, at this stage of method 300, the relevant exposed structures shown in FIGS. 21A–22B include the fourth dielectric layer 234, the first liner 232, the second liner 239, the isolation feature 203, and the backside source contact 242. Applicant should clarify and correctly identify the components having coplanar top surfaces.
• Paragraph [0048] recites “an MBC transistor according the present disclosure.” The phrase should be corrected to “an MBC transistor according to the present disclosure.”
• Paragraph [0051] first introduces both “a first substrate portion over the first epitaxial feature” and “a second substrate portion over the second epitaxial feature,” but subsequently recites “top surfaces of the first dielectric layer and the substrate portion are coplanar.” Because two different substrate portions were previously introduced, the expression “the substrate portion” is ambiguous. Based on the process described in paragraphs [0036]–[0040], the expression apparently should identify “the second substrate portion.”
• Paragraph [0051] further recites “anisotropically recessing the second liner to expose a portion the second epitaxial feature.” The phrase should be corrected to “anisotropically recessing the second liner to expose a portion of the second epitaxial feature.”
• Paragraph [0051] later recites “the selectively recessing the substrate portion to expose the second epitaxial feature.” Because both first and second substrate portions were previously introduced, Applicant should clarify the recitation by identifying the applicable substrate portion, apparently “the second substrate portion.” The phrase should also be grammatically corrected, for example, to “selectively recessing the second substrate portion to expose the second epitaxial feature.”
• Paragraph [0053] recites planarizing the workpiece such that top surfaces of the first nitride liner, the first dielectric layer, the isolation feature, and the “second epitaxial feature” are coplanar. This recitation appears inconsistent with paragraph [0040] and FIGS. 16A–16B, which indicate that the source base portion 202SB remains over the source epitaxial feature 212S and is exposed by the planarization process. Applicant should clarify whether “second epitaxial feature” was intended to recite the “second semiconductor base portion,” and should revise the paragraph consistently with the disclosed process and drawings.
• Paragraphs [0021], [0026], [0030], [0045], and [0046] list “(TiN)” as a material without identifying the corresponding material name. Each occurrence should be corrected to “titanium nitride (TiN)” for clarity and consistency with the other listed materials.
Applicant is required to correct the foregoing informalities and inconsistencies throughout the specification without introducing new matter.
Claim Objections
Claims 5, 6, 13, 16, and 17 are objected to because of the following informalities. Appropriate correction is required.
• Claim 5 recites two separate “wherein” clauses without a coordinating conjunction. The relevant portion should be revised, for example, to recite:
wherein the first dielectric liner comprises an oxygen-atom-free dielectric material; and
wherein the bottom dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG).
• Claim 6 recites that “the oxygen-atom-free dielectric material comprises silicon nitride, silicon carbide, silicon carbonitride,” without a coordinating conjunction identifying whether the listed materials are alternatives or are all required. The description presents these materials as alternatives. See paragraph [0038]. If alternatives are intended, claim 6 should be revised to recite:
wherein the oxygen-atom-free dielectric material comprises silicon nitride, silicon carbide, or silicon carbonitride.
Without “or,” claim 6 may be read as requiring the oxygen-atom-free dielectric material to comprise all three listed materials.
• Claim 13 omits appropriate punctuation after the transitional phrase “further comprising” Claim 13 should be revised to recite:
The device structure of claim 12, further comprising:
• Claim 16 recites that “the bottom dielectric layer comprises silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride,” without a coordinating conjunction identifying whether the listed materials are alternatives or are all required. The description presents these materials as alternatives. See paragraph [0018]. If alternatives are intended, claim 16 should be revised to recite:
wherein the bottom dielectric layer comprises silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, or silicon carbonitride.
Without “or,” claim 16 may be read as requiring the bottom dielectric layer to comprise all five listed materials.
• Claim 17 recites “a gate structure disposed over a bottom dielectric layer and wrapping around each of the vertical stack of nanostructures.” The expression “each of the vertical stack” is grammatically incorrect because “each” should refer to the individual nanostructures within the stack, rather than to the singular stack itself. Claim 17 should be revised, for example, to recite:
a gate structure disposed over a bottom dielectric layer and wrapping around each nanostructure of the vertical stack of nanostructures.
Applicant is required to correct the foregoing informalities without introducing new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 17-10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 17, the claim first recites:
“a gate structure disposed over a bottom dielectric layer”
and subsequently recites:
“wherein the gate structure is vertically spaced apart from the backside dielectric layer and the backside source contact by a bottom dielectric layer.”
The second occurrence of “a bottom dielectric layer” lacks a clear relationship to the previously recited bottom dielectric layer. Specifically, it is unclear whether the second-recited “a bottom dielectric layer” refers to the same bottom dielectric layer over which the gate structure is disposed or introduces a separate, additional bottom dielectric layer. These interpretations result in different claim scopes because one interpretation requires a single bottom dielectric layer satisfying both recited relationships, whereas the other permits or requires two different bottom dielectric layers. Accordingly, the metes and bounds of the claimed structure are unclear.
Claim 17 further recites:
“a gate structure disposed over a bottom dielectric layer and wrapping around each of the vertical stack of nanostructures.”
The phrase “each of the vertical stack of nanostructures” is unclear because “each” grammatically modifies the singular “vertical stack,” rather than the individual nanostructures within the stack. Consequently, it is unclear whether the gate structure is required to wrap around each individual nanostructure of the vertical stack or around the vertical stack collectively.
Regarding claims 18-20, because of their dependency on claim 17, these claims are also objected for the reasons set forth above with respect to claim 17.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1-8 and 10-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,125,852 (“Pat-852”) in view of Frougier et al. (US 20210043727; “Frougier”).
Regarding claim 1, claim 1 of Pat-852 teaches a structure comprising an isolation feature; first, second, and third dielectric fins disposed over the isolation feature; a first epitaxial feature sandwiched between the first and second dielectric fins; a second epitaxial feature sandwiched between the second and third dielectric fins; a backside dielectric plug extending through the isolation feature to contact the first epitaxial feature; and a backside contact extending through the isolation feature to contact the second epitaxial feature by way of a silicide layer. By virtue of their respective placement between successively arranged dielectric fins disposed over the isolation feature, the first and second epitaxial features are disposed alongside one another over the isolation feature.
But Claim 1 of Pat-852 does not expressly teach:
• a first plurality of nanostructures interfacing a sidewall of the first epitaxial feature; and
• a second plurality of nanostructures interfacing a sidewall of the second epitaxial feature.
However, Frougier teaches a semiconductor structure comprising a row of gate-all-around field-effect transistors connected in series by shared source/drain regions 115 (FIG. 1A and paragraph [0044]). The source/drain regions 115 comprise epitaxial monocrystalline semiconductor material and are disposed above isolation layer 105 (paragraph [0045]).
Frougier further teaches multiple semiconductor nanosheets 110 extending laterally between the epitaxial source/drain regions 115 and stacked vertically above one another (paragraphs [0046]–[0047]). As shown in FIG. 1A, a first plurality of vertically stacked semiconductor nanosheets 110, corresponding to the leftmost stack, interfaces a sidewall of a first epitaxial source/drain region 115. A second plurality of vertically stacked semiconductor nanosheets 110, corresponding to the rightmost stack, interfaces a sidewall of a second epitaxial source/drain region 115.
More particularly, each nanosheet 110 includes end portions 112 immediately adjacent to the respective source/drain regions 115, with junctions formed between the end portions 112 and the source/drain regions 115 (paragraph [0048]). Frougier also teaches epitaxially growing the source/drain regions 115 on exposed vertical surfaces of the semiconductor material that subsequently forms the nanosheets 110, thereby further establishing that the nanosheets interface the sidewalls of the epitaxial source/drain regions (paragraphs [0082] and [0086]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first and second epitaxial features of claim 1 of Pat-852 to interface respective pluralities of vertically stacked semiconductor nanosheets, as taught by Frougier, in order to implement the epitaxial features as source/drain regions of nanosheet-type gate-all-around transistors. Frougier teaches that nanosheet-type gate-all-around transistors improve device drive current and electrostatic control and permit further device scaling (paragraph [0002]). The modification would have amounted to the predictable use of a known nanosheet-channel arrangement with the epitaxial features claimed in Pat-852.
Accordingly, claim 1 would have been obvious over claim 1 of Pat-852 in view of Frougier.
Regarding claim 2, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above. Claim 1 of Pat-852 further teaches a first dielectric fin, a second dielectric fin, and a third dielectric fin disposed over the isolation feature, wherein the first epitaxial feature is sandwiched between the first dielectric fin and the second dielectric fin, and wherein the second epitaxial feature is sandwiched between the second dielectric fin and the third dielectric fin.
Accordingly, claim 2 would have been obvious over claim 1 of Pat-852 in view of Frougier.
Regarding claim 3, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above, and claim 1 of Pat-852 further teaches the limitations of claim 2. Claim 8 of Pat-852 further teaches that the first dielectric fin, the second dielectric fin, and the third dielectric fin comprise hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride.
Accordingly, claim 3 would have been obvious over claims 1 and 8 of Pat-852 in view of Frougier.
Regarding claim 4, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above. Claims 1 and 2 of Pat-852 further teach that the backside dielectric plug comprises a first dielectric liner in contact with the isolation feature and the first epitaxial feature, and a bottom dielectric layer spaced apart from the isolation feature and the first epitaxial feature by the first dielectric liner.
Accordingly, claim 4 would have been obvious over claims 1 and 2 of Pat-852 in view of Frougier.
Regarding claim 5, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above, and claims 1 and 2 of Pat-852 further teach the limitations of claim 4. Claim 3 of Pat-852 further teaches that the first dielectric liner comprises an oxygen-atom-free dielectric material and that the bottom dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG).
Accordingly, claim 5 would have been obvious over claims 1–3 of Pat-852 in view of Frougier.
Regarding claim 6, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above, and claims 1–3 of Pat-852 further teach the limitations of claims 4 and 5. Claim 4 of Pat-852 further teaches that the oxygen-atom-free dielectric material comprises silicon nitride, silicon carbide, or silicon carbonitride.
Accordingly, claim 6 would have been obvious over claims 1–4 of Pat-852 in view of Frougier.
Regarding claim 7, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above. Claims 5 and 6 of Pat-852 further teach that the backside contact comprises a second dielectric liner in contact with the isolation feature and a metal fill layer spaced apart from the isolation feature by the second dielectric liner and in direct contact with the silicide layer disposed between the backside contact and the second epitaxial feature.
Accordingly, claim 7 would have been obvious over claims 1 and 5–6 of Pat-852 in view of Frougier.
Regarding claim 8, claim 1 of Pat-852 in view of Frougier teaches the structure of claim 1 as set forth above, and claims 5 and 6 of Pat-852 further teach the limitations of claim 7. Claim 7 of Pat-852 further teaches that the second dielectric liner comprises silicon nitride, silicon carbide, or silicon carbonitride.
Accordingly, claim 8 would have been obvious over claims 1 and 5–7 of Pat-852 in view of Frougier.
Regarding claim 10, claim 9 of Pat-852 teaches a device structure comprising:
• an isolation feature;
• first, second, and third dielectric fins disposed over the isolation feature;
• a first epitaxial feature sandwiched between the first and second dielectric fins;
• a second epitaxial feature sandwiched between the second and third dielectric fins;
• a backside dielectric plug extending through the isolation feature to contact the first epitaxial feature;
• a backside contact extending through the isolation feature to contact the second epitaxial feature by way of a silicide layer;
• a contact etch stop layer disposed over top surfaces of the first epitaxial feature and the second epitaxial feature;
• a first dielectric layer disposed over the contact etch stop layer;
• a first frontside contact extending through the first dielectric layer and the contact etch stop layer to contact the first epitaxial feature; and
• a second frontside contact extending through the first dielectric layer and the contact etch stop layer to contact the second epitaxial feature.
By virtue of the first and second epitaxial features being positioned between successively arranged dielectric fins disposed over the isolation feature, the first and second epitaxial features are disposed alongside one another over the isolation feature. The additional dielectric fins recited in claim 9 of Pat-852 do not distinguish instant claim 10 because claim 10 employs the open transitional term “comprising.”
But Claim 9 of Pat-852 does not expressly teach:
• a first plurality of nanostructures interfacing a sidewall of the first epitaxial feature; and
• a second plurality of nanostructures interfacing a sidewall of the second epitaxial feature.
However, Frougier teaches a semiconductor structure comprising a row of gate-all-around field-effect transistors connected in series by shared source/drain regions 115, as illustrated in FIG. 1A and described in paragraph [0044]. Frougier teaches that source/drain regions 115 comprise epitaxial monocrystalline semiconductor material and are disposed above and immediately adjacent to isolation layer 105 (paragraph [0045]).
Frougier further teaches multiple semiconductor nanosheets 110 extending laterally between epitaxial source/drain regions 115 and stacked vertically above one another (paragraphs [0046]–[0047]). As shown in FIG. 1A, a first plurality of vertically stacked semiconductor nanosheets 110, corresponding to the leftmost stack, interfaces a sidewall of a first epitaxial source/drain region 115. A second plurality of vertically stacked semiconductor nanosheets 110, corresponding to the rightmost stack, interfaces a sidewall of a second epitaxial source/drain region 115.
More particularly, each nanosheet 110 includes end portions 112 immediately adjacent to the respective source/drain regions 115, with junctions formed between the end portions 112 and source/drain regions 115 (paragraph [0048]). Frougier additionally teaches epitaxially growing source/drain regions 115 on exposed vertical surfaces of the semiconductor material that subsequently forms nanosheets 110, thereby establishing that the nanosheets interface the sidewalls of the epitaxial source/drain regions (paragraphs [0082] and [0086]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first and second epitaxial features claimed in claim 9 of Pat-852 to interface respective pluralities of vertically stacked semiconductor nanosheets, as taught by Frougier, in order to implement the first and second epitaxial features as source/drain regions of nanosheet-type gate-all-around transistors. Frougier teaches that nanosheet-type gate-all-around transistors improve device drive current and electrostatic control and permit further device scaling (paragraph [0002]). The modification would have amounted to the predictable use of a known nanosheet-channel arrangement with the epitaxial features claimed in Pat-852.
Accordingly, claim 10 would have been obvious over claim 9 of Pat-852 in view of Frougier.
Regarding claim 11, claim 9 of Pat-852 in view of Frougier teaches the device structure of claim 10 as set forth above. Claim 10 of Pat-852 further teaches a second dielectric layer disposed over the first frontside contact, wherein top surfaces of the first dielectric layer and the second dielectric layer are coplanar.
Accordingly, claim 11 would have been obvious over claims 9 and 10 of Pat-852 in view of Frougier.
Regarding claim 12, claim 9 of Pat-852 in view of Frougier teaches the device structure of claim 10 as set forth above. Claim 9 of Pat-852 further teaches a first dielectric fin, a second dielectric fin, and a third dielectric fin disposed over the isolation feature, wherein the first epitaxial feature is sandwiched between the first dielectric fin and the second dielectric fin along a first direction, and wherein the second epitaxial feature is sandwiched between the second dielectric fin and the third dielectric fin along the first direction.
Accordingly, claim 12 would have been obvious over claim 9 of Pat-852 in view of Frougier.
Regarding claim 13, claim 9 of Pat-852 in view of Frougier teaches the device structure of claim 10 as set forth above, and claim 9 of Pat-852 further teaches the limitations of claim 12. Claim 11 of Pat-852 further teaches a plurality of nanostructures extending lengthwise along a second direction perpendicular to the first direction; a gate structure wrapping around each of the plurality of nanostructures; and sidewalls of the plurality of nanostructures being in contact with the second epitaxial feature.
Accordingly, claim 13 would have been obvious over claims 9 and 11 of Pat-852 in view of Frougier.
Regarding claim 14, claim 9 of Pat-852 in view of Frougier teaches the device structure of claim 10 as set forth above, and claims 9 and 11 of Pat-852 further teach the limitations of claims 12 and 13. Claim 12 of Pat-852 further teaches that the gate structure is spaced apart from the second epitaxial feature by a plurality of inner spacer features.
Accordingly, claim 14 would have been obvious over claims 9 and 11–12 of Pat-852 in view of Frougier.
Regarding claim 15, claim 9 of Pat-852 in view of Frougier teaches the device structure of claim 10 as set forth above, and claims 9 and 11–12 of Pat-852 further teach the limitations of claims 12–14. Claim 13 of Pat-852 further teaches a bottom dielectric layer disposed below and in contact with the gate structure, wherein the bottom dielectric layer is in contact with a bottommost one of the plurality of inner spacer features.
Accordingly, claim 15 would have been obvious over claims 9 and 11–13 of Pat-852 in view of Frougier.
Regarding claim 16, claim 9 of Pat-852 in view of Frougier teaches the device structure of claim 10 as set forth above, and claims 9 and 11–13 of Pat-852 further teach the limitations of claims 12–15. Claim 15 of Pat-852 further teaches that the bottom dielectric layer comprises silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, or silicon carbonitride.
Accordingly, claim 16 would have been obvious over claims 9, 11–13, and 15 of Pat-852 in view of Frougier.
Claims 17-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 11,804,486 (“Pat-486”).
Regarding claim 17, claim 1 of Pat-486 teaches a semiconductor structure comprising a source feature and a drain feature; a vertical stack of nanostructures extending between the source feature and the drain feature; a gate structure disposed over a bottom dielectric layer and wrapping around each nanostructure of the vertical stack of nanostructures; a backside dielectric layer underlying the bottom dielectric layer and extending continuously below the drain feature; and a backside source contact extending through the bottom dielectric layer and the backside dielectric layer to electrically couple to the source feature.
The backside dielectric layer extending continuously below the drain feature teaches the drain feature disposed over the backside dielectric layer. The backside source contact extending through the backside dielectric layer to electrically couple to the source feature teaches the source feature disposed over the backside source contact.
Claim 1 of Pat-486 further teaches the gate structure disposed over the bottom dielectric layer while the backside dielectric layer underlies the bottom dielectric layer. Thus, the gate structure is vertically spaced apart from the backside dielectric layer by the bottom dielectric layer. The backside source contact extends through the bottom dielectric layer in a region adjacent to the gate structure. Under the broadest reasonable interpretation of the final limitation of claim 17, this arrangement teaches the gate structure spaced apart from the adjacent backside source contact by the bottom dielectric layer.
Regarding claim 18, claim 1 of Pat-486 teaches the semiconductor structure of claim 17 as set forth above. Claim 2 of Pat-486 further teaches a first dielectric liner extending continuously from between the backside source contact and the backside dielectric layer to between the backside source contact and the bottom dielectric layer, as well as from between the backside source contact and the bottom dielectric layer to between the source feature and the backside source contact.
Thus, under the broadest reasonable interpretation being applied to claim 18, the first liner spaces the backside dielectric layer from the backside source contact and extends along the interfaces between the backside source contact, the backside dielectric layer, and the bottom dielectric layer, thereby teaching the claimed dielectric-liner relationship.
Accordingly, claim 18 is not patentably distinct from claims 1 and 2 of Pat-486.
Allowable Subject Matter
Claims 1-20 would be allowable if overcome the nonstatutory double patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, Frougier et al. (US 20210043727; “Frougier”) discloses an isolation layer 105 and epitaxial source/drain regions 115 disposed over the isolation layer (FIG. 1A; paragraphs [0043]–[0045]). Frougier further discloses multiple semiconductor nanosheets 110 extending laterally between respective source/drain regions 115 and interfacing the sidewalls thereof (paragraphs [0046]–[0048]). Thus, Frougier discloses first and second epitaxial features and respective pluralities of nanostructures interfacing sidewalls of the epitaxial features.
Reznicek et al. (US 20190378842; in the IDS on 9/27/24; “Reznicek”) discloses a polycrystalline semiconductor electrode 20 positioned in a trench extending through portions of an SOI structure and a doped polycrystalline semiconductor strap 36 connecting electrode 20 to a source/drain region 36C (FIG. 14; paragraphs [0045]–[0049], [0080]–[0081], and [0096]). Even if electrode 20 is broadly regarded as a backside contact, Reznicek does not disclose that electrode 20 contacts an epitaxial feature by way of a silicide layer.
Neither Frougier nor Reznicek, alone or in combination, teaches or suggests the particular arrangement recited in claim 1 in which a backside dielectric plug extends through an isolation feature to contact a first epitaxial feature, while a backside contact separately extends through the isolation feature to contact a second epitaxial feature by way of a silicide layer. In particular, the prior art of record does not teach or suggest the claimed asymmetric backside arrangement providing a dielectric plug in contact with one epitaxial feature and a silicide-coupled backside contact in contact with an adjacent epitaxial feature through the same isolation feature.
Accordingly, claim 1 would be allowable if the outstanding nonstatutory double patenting rejection is overcome.
Regarding claim 10, Kang et al. (US 20200083219; “Kang”) discloses an isolation feature corresponding to third insulation portion 554C of bottom insulation structure 554 and a plurality of epitaxial source/drain features 530 disposed thereover (FIG. 30D; paragraphs [0060]–[0063] and [0119]). Kang further discloses respective nanosheet stack structures NSS, each comprising a plurality of nanosheets N1–N4 interfacing sidewalls of adjacent epitaxial source/drain features 530.
Kang also discloses a protective insulation layer 142, corresponding to the claimed contact etch stop layer, disposed over the source/drain features; an inter-gate insulation layer 144 disposed over protective insulation layer 142; and respective frontside contact plugs 184 extending through the insulation layers and electrically contacting corresponding source/drain features 530 by way of metal silicide layers 182 (FIG. 30D; paragraphs [0040], [0044]–[0045], and [0119]).
Reznicek et al. (US 20190378842; in the IDS on 9/27/24; “Reznicek”) discloses a polycrystalline semiconductor electrode 20 positioned in a trench extending through portions of an SOI structure and a doped polycrystalline semiconductor strap 36 connecting electrode 20 to a source/drain region 36C (FIG. 14; paragraphs [0045]–[0049], [0080]–[0081], and [0096]). Even if electrode 20 is broadly regarded as a backside contact extending through an isolation feature, Reznicek does not disclose that the electrode contacts an epitaxial feature by way of a silicide layer.
Neither Kang nor Reznicek, alone or in combination, teaches or suggests the particular arrangement recited in claim 10 in which a backside dielectric plug extends through an isolation feature to contact a first epitaxial feature, while a separate backside contact extends through the isolation feature to contact an adjacent second epitaxial feature by way of a silicide layer. In particular, the prior art of record does not teach or suggest the claimed asymmetric backside arrangement providing a dielectric plug in contact with one epitaxial feature and a silicide-coupled backside contact in contact with an adjacent epitaxial feature, together with the recited frontside contacts.
Accordingly, claim 10 would be allowable if the outstanding nonstatutory double patenting rejection is overcome.
Regarding claim 17, Kang et al. (US 20200083219; “Kang”) discloses adjacent epitaxial source/drain features 530 and a vertical stack NSS of nanosheets N1–N4 extending between the adjacent source/drain features (FIG. 30D; paragraphs [0060]–[0063] and [0119]). Kang further discloses a gate structure 160 disposed over a bottom insulation structure 554. Gate structure 160 surrounds at least portions of the nanosheets and completely surrounds nanosheets N2–N4, while the lower surface of nanosheet N1 is not surrounded by the gate structure (paragraphs [0031] and [0062]).
Reznicek et al. (US 2019/0378842 A1; in the IDS on 9/27/24; “Reznicek”) discloses a polycrystalline semiconductor electrode 20 positioned within a trench of an SOI structure and connected to a source/drain region 36C by a doped polycrystalline semiconductor strap 36 (FIG. 14; paragraphs [0045]–[0049], [0080]–[0081], and [0096]). However, electrode 20 is an electrode of an eDRAM cell and is not disclosed as a backside source contact extending through a backside dielectric layer.
Neither Kang nor Reznicek, alone or in combination, teaches or suggests a backside source contact extending through a backside dielectric layer and positioned below a source feature, in combination with a gate structure vertically spaced apart from both the backside dielectric layer and the backside source contact by a bottom dielectric layer. In particular, the prior art of record does not teach or suggest the claimed vertical arrangement in which the bottom dielectric layer vertically separates the gate structure from both the backside dielectric layer and the backside source contact, while the backside source contact extends through the backside dielectric layer toward the source feature.
Accordingly, claim 17 would be allowable if amended to overcome the outstanding rejection under 35 U.S.C. 112(b) and if the nonstatutory double patenting rejection is overcome.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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