DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Chinese Patent Application No. CN202311575226.X, filed on 11/23/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “TRENCH SEMICONDUCTOR POWER DEVICE COMPRISING BACK-TO-BACK DIODES FOR ELECTROSTATIC DISCHARGE PROTECTION”.
Claim Objections
Claim 1 is objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
On line 13 of claim 1, the claim recites that “a first part abutting against the body doped region”. According to the disclosure, there is an insulating layer (insulating layer 115) between the first part (120_1) and the body doped region (106) in all the embodiments illustrated in the figures. The most common interpretation of the verb “abut” implies sharing a border or direct physical contact (see Merriam-Webster dictionary definitions: (1) to border on : to touch along an edge; (2) to cause to touch or lean for support; (3): to touch along a border or with a projecting part; (4) to terminate at a point of contact; (5): to lean for support). Therefore, for preventing any misinterpretation of the claim 1 and properly describing the invention, the Examiner recommends to amend the phrase “abutting against” to “adjacent to”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yilmaz (US 2016/0260814 A1).
Regarding claim 1, Yilmaz teaches a trench-type semiconductor power device (MOSFET device, Figs. 11A-B, [0055]-[0056]) comprising:
a substrate (semiconductor substrate 105, Fig. 11A, [0055]) having a first conductivity type (N-type, [0039]: “N+ substrate 105”);
a lightly doped region (N-type epitaxial layer 110, Fig. 11A, [0039]) located on the substrate (semiconductor substrate 105, Fig. 11A) and having the first conductivity type (N-type);
a body doped region (P-body regions 140, Fig. 11A, [0037]) located in the lightly doped region (N-type epitaxial layer 110, Fig. 11A) and distant from the substrate (semiconductor substrate 105, Fig. 11A), the body doped region (P-body regions 140, Fig. 11A) having a second conductivity type (P-type);
a source doped region (source region 150, Fig. 11A, [0037]) located in the body doped region (P-body regions 140, Fig. 11A) and distant from the substrate (semiconductor substrate 105, Fig. 11A), the source doped region (source region 150, Fig. 11A) having the first conductivity type (N-type, [0052]: “N+ source regions 150”); and
a trench structure (trench 119, which is labeled as trench structure in Illustrative Fig. 1, which is an annotated version of Yilmaz’s Figs. 11A and 11B) having a first depth (first depth, Illustrative Fig. 1) in a first direction (first direction, Illustrative Fig. 1) extending from the source doped region (source region 150, Illustrative Fig. 1) to the substrate (semiconductor substrate 105, Illustrative Fig. 1) and comprising a first semiconductor layer (comprising P-type polysilicon layer 135-P and N-type polysilicon layer 135-N, Illustrative Fig. 1, [0055]) extending in a second direction (second direction, Illustrative Fig. 1), the first direction (vertical direction, which is labeled as first direction in Illustrative Fig. 1) being perpendicular to the second direction (second direction, Illustrative Fig. 1), wherein the first semiconductor layer (comprising P-type polysilicon layer 135-P and N-type polysilicon layer 135-N, Illustrative Fig. 1) comprises:
PNG
media_image1.png
713
1430
media_image1.png
Greyscale
a first part (N-type polysilicon layer 135-N, which is labeled as first part in Illustrative Fig. 1) abutting against the body doped region (P-body regions 140, Illustrative Fig. 1) and the source doped region (source region 150, Illustrative Fig. 1) and serving as a gate electrode (Illustrative Fig. 1: N-type polysilicon layer 135-N is connected to the gate electrode, and therefore serves as a gate with the surrounding source regions) having the first conductivity type (N-type); and
a second part (comprising P-type polysilicon layer 135-P and N-type polysilicon layer 135-N towards second direction, which is shown as second part in Illustrative Fig. 1) extending in the second direction (second direction, Illustrative Fig. 1) and distant from the source doped region (source region 150, which is labeled as source doped region in Illustrative Fig. 1), the second part (second part, Illustrative Fig. 1) comprising a plurality of first doped regions (N-type polysilicon layers 135-N in second part , Illustrative Fig. 1) having the first conductivity type (N-type) and a plurality of second doped regions (P-type polysilicon layers 135-P in second part , Illustrative Fig. 1) having the second conductivity type (P-type), wherein the plurality of first doped regions (N-type polysilicon layers 135-N in second part , Illustrative Fig. 1) and the plurality of second doped regions (P-type polysilicon layers 135-P in second part , Illustrative Fig. 1) are staggered (along the second direction in Illustrative Fig. 1) to form a first diode string (see first diode string as shown in Illustrative Fig. 1) having one or more back-to-back diodes (Illustrative Fig. 1: first diode string comprises back-to-back diodes);
wherein a first end of the first diode string (first end, Illustrative Fig. 1) is electrically connected to the gate electrode (gate (G), Illustrative Fig. 1, [[0056]-[0057]: polysilicon 135-N of the first part is at the gate potential), and a second end of the first diode string (second end, Illustrative Fig. 1) is electrically connected to the source doped region ([0056]-[0057]: connected to source (S) (Illustrative Fig. 1), and therefore connected to source doped region) through a first connection structure (first connection structure, Illustrative Fig. 1).
Regarding claim 2, Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 1, wherein interfaces between each second doped region (P-type polysilicon layers 135-P in second part, Illustrative Fig. 1) and two first doped regions (N-type polysilicon layers 135-N in second part, Illustrative Fig. 1) adjacent to the second doped region (P-type polysilicon layers 135-P in second part, Illustrative Fig. 1) respectively form a first PN junction (first PN junction, Illustrative Fig. 1) and a second PN junction (second PN junction, Illustrative Fig. 1) of each of the one or more back-to-back diodes (first diode string, Illustrative Fig. 1.
Regarding claim 4, Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 1, wherein the first semiconductor layer (comprising P-type polysilicon layer 135-P and N-type polysilicon layer 135-N, Illustrative Fig. 1) comprises polysilicon ([0055]: “polysilicon”), silicon carbide, gallium nitride, gallium oxide or diamond-based materials.
Regarding claim 5, Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 1, wherein the trench structure (trench structure, Illustrative Fig. 1) further comprises an insulating layer (gate oxide 132, Illustrative Fig. 1 (see also Fig. 10D), [0050]) surrounding the first semiconductor layer (comprising P-type polysilicon layer 135-P and N-type polysilicon layer 135-N, Illustrative Fig. 1) so that the first semiconductor layer (comprising P-type polysilicon layer 135-P and N-type polysilicon layer 135-N, Illustrative Fig. 1) is separated from the lightly doped region (N-type epitaxial layer 110, Illustrative Fig. 1), the body doped region (P-body regions 140, Illustrative Fig. 1) and the source doped region (source doped region, Illustrative Fig. 1).
Regarding claim 6, Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 1, further comprising:
an electrostatic discharge protection structure (the structure labeled as ESD structure in Illustrative Fig. 1, which is identical in structure to the first diode string, [0056]) located above or in a same horizontal plane (Illustrative Fig. 1: same horizontal plane) as the first semiconductor layer (first semiconductor layer, Illustrative Fig. 1), wherein the electrostatic discharge protection structure (ESD structure, Illustrative Fig. 1) comprises:
a second semiconductor layer (second semiconductor layer, Illustrative Fig. 1) that comprises a plurality of third doped regions (N-type polysilicon layers 135-N in second semiconductor layer, Illustrative Fig. 1) having the first conductivity type (N-type) and a plurality of fourth doped regions (P-type polysilicon layers 135-P in second semiconductor layer, Illustrative Fig. 1) having the second conductivity type (P-type);
wherein the plurality of third doped regions (N-type polysilicon layers 135-N in second semiconductor layer, Illustrative Fig. 1) and the plurality of fourth doped regions (P-type polysilicon layers 135-P in second semiconductor layer, Illustrative Fig. 1) are staggered (along the second direction in Illustrative Fig. 1) to form a second diode string (see second diode string as shown in Illustrative Fig. 1) having one or more back-to-back diodes (Illustrative Fig. 1: second diode string comprises back-to-back diodes); and
wherein a first end of the second diode string (top end of the second diode string in Illustrative Fig. 1) is electrically connected to the source doped region ([0056]-[0057]: connected to source (S) (Illustrative Fig. 1), and therefore connected to source doped region) through the first connection structure (first connection structure, Illustrative Fig. 1) and a second end of the second diode (top end of the second diode string in Illustrative Fig. 1) string is electrically connected to the first end of the first diode string (first end, Illustrative Fig. 1) through a second connection structure (second connection structure, Illustrative Fig. 1).
Regarding claim 7, Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 6, wherein the first semiconductor layer (first semiconductor layer, Illustrative Fig. 1) is separated from the electrostatic discharge protection structure (ESD structure, Illustrative Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2016/0260814 A1) as applied to claims 1-2 and 4-7 above, and further in view of Kang (US 2017/0194316 A1).
Regarding claim 3, Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 1, wherein the first end of the first diode string (first end, Illustrative Fig. 1) is electrically connected to a second connection structure (second connection structure, Illustrative Fig. 1).
Yilmaz, however, does not teach that the first semiconductor layer further comprises a third part that extends in the second direction away from the source doped region, the third part being disposed between the first part and the second part and having the first conductivity type, wherein the third part of the first semiconductor layer forms a gate resistor.
Kang, on the other hand, teaches a trench-type semiconductor device (semiconductor device 100 (e.g., trench MOSFET), Figs. 2A-D, [0039]) with a first semiconductor layer (gate electrode 42, Figs. 2C -D, [0043]: while Kang does not explicitly disclose that the gate electrode is a semiconductor, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the gate electrode is a semiconductor, as the gate electrode is separate than the gate metal disclosed in Kang, and an extension of the gate electrode is used as a resistor (see below) in a trench structure (trench 70, Figs. 2C-D, [0043]) and a diode string (diode 50, Fig. 2D, [0041]: “the diode 50 may be able to clamp a high ESD voltage applied to the gate pad 40”), wherein the first end of the diode string is connected to the source and the second end is connected to the gate electrode (see Fig. 1C for the equivalent circuit diagram). Kang further teaches that the first semiconductor layer (gate electrode 42, Fig. 2D) further comprises a third part (gate electrode extension 42a on the left side of the diode 50, see the structure labeled as third part in Illustrative Fig. 2, which is an annotated version of Kang’s Fig. 2D) that extends in the second direction (second direction (analogous to the second direction of Yilmaz), Illustrative Fig. 2) away from the source doped region (while not shown in any figures, the source region is at the left side of the gate electrode extension 72a (below the source metal 30) in Illustrative Fig. 2 (see also Figs 2B-C), [0049]-[0050]), the third part (third part, Illustrative Fig. 2) being disposed between the first part (while not shown in Illustrative Fig. 1, the location of the first part is indicated by an arrow in Illustrative Fig. 2) and the second part (second part, Illustrative Fig. 2) and having the first conductivity type (same conductivity type as the gate electrode 42, as the gate electrode extension 42a is an extension of the gate electrode 42 towards second direction, Illustrative Fig. 2), wherein the third part of the first semiconductor layer (third part, Illustrative Fig. 2) forms a gate resistor ([0045]: “the extended gate electrode 42a may function as a resistor between the gate pad 40 and the cell gate electrode”).
PNG
media_image2.png
689
922
media_image2.png
Greyscale
Kang further discloses that “the extended gate electrode 42a may function as a resistor between the gate pad 40 and the cell gate electrode, and hence may delay the ESD voltage and current flowing in from the low voltage input terminal to the transistor cell region. While the in-flowing voltage and/or current are delayed, the ESD voltage and current may be discharged to the ground via the diode 50, and damage due to the ESD voltage and current may be prevented” ([0045]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the trench-type semiconductor power device of Yilmaz by elongating the first semiconductor layer towards the second direction (Illustrative Fig. 1) by including a third part (by extending the N-type polysilicon layer 135-N of the first part along the second direction) between the first part and the second part, as taught by Kang, to form a gate resistor, which would provide the benefit of improving the electrostatic discharge protection. Thus, the combination of Yilmaz and Kang meets all the limitations of claim 3.
Regarding claim 8, while Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 6,
Yilmaz does not teach that the electrostatic discharge protection structure is located above the first semiconductor layer, and the second part of the first semiconductor layer abuts against the second semiconductor layer of the electrostatic discharge protection structure.
Kang, on the other hand, teaches a trench-type semiconductor device (semiconductor device 100 (e.g., trench MOSFET), Figs. 2A-D, [0039]) with a first semiconductor layer (gate electrode 42, Figs. 2C -D, [0043]: while Kang does not explicitly disclose that the gate electrode is a semiconductor, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the gate electrode is a semiconductor, as the gate electrode is separate than the gate metal disclosed in Kang, and an extension of the gate electrode is used as a resistor (see claim 3 rejection above for description) in a trench structure (trench 70, Figs. 2C-D, [0043]) and an electrostatic discharge protection structure (diode 50, Fig. 2D, [0041]: “the diode 50 may be able to clamp a high ESD voltage applied to the gate pad 40”) comprising a second semiconductor layer (first doping region 51 and second doping region 52, Fig. 2D, [0052]), wherein the first end of the electrostatic discharge structure is connected to the source and the second end is connected to the gate electrode (see Fig. 1C for the equivalent circuit diagram). Kang further teaches that the electrostatic discharge protection structure (diode 50, Fig. 2D) is located above the first semiconductor layer (gate electrode 42 and gate electrode extension 42a, Figs. 2D), and the second part of the first semiconductor layer (the portion of the gate electrode extension 42a under the diode 50) abuts against the second semiconductor layer (bottom surfaces of the first doping region 51 and second doping region 52, Fig. 2D) of the electrostatic discharge protection structure (diode 50, Fig. 2D).
Kang further discloses that “due to the limited space issues in designing and manufacturing semiconductor integrated circuit (IC) devices, it is challenging to allocate sufficient space for effective ESD protection circuitry” ([0003]), and forming the electrostatic discharge structure above the gate electrode extension provides the benefit of keeping the device size small by using the extended gate as a resistor (which eliminates the need to include a resistor in the device) ([0004] and [0042]) and limiting the lateral size of the device. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the trench-type semiconductor power device of Yilmaz so that the electrostatic discharge protection structure is above the first semiconductor layer (rather than next to the first semiconductor layer from plan view, which would increase the lateral size), as taught by Kang to provide the benefit of keeping the device size small.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2016/0260814 A1) as applied to claims 1-2 and 4-7 above, and further in view of Challa (US 2006/0214222 A1).
Regarding claim 9, while Yilmaz teaches the trench-type semiconductor power device (MOSFET device, Figs. 11A-B) of claim 1,
Yilmaz does not teach that the trench-type semiconductor power device comprises:
a shielding structure surrounding the trench structure and being separated from the first diode string by penetrating through the lightly doped region and the body doped region, the shielding structure comprising a second semiconductor layer, wherein the second semiconductor layer comprises:
a fourth part having the first conductivity type and being connected to the source doped region through the first connection structure;
wherein in the first direction, a depth of the shielding structure is greater than the first depth.
Challa, on the other hand, teaches a trench-type semiconductor power device (dual trench power MOSFET 200, Fig. 2A, [0113]) with a first semiconductor layer (gate trench conductive layer 210, Fig. 2A, [0114]; “doped polysilicon” ([0109]) in a trench structure (gate trench 202, Fig. 2A, [0115]) as a gate (gate G, Fig. 2A). Challa further teaches that the trench-type semiconductor power device comprises
a shielding structure (shield trenches 220, Fig. 2A, [0113]) surrounding (from left and right in Fig. 2A) the trench structure (gate trench 202, Fig. 2A) and being separated from the first diode string (gate trench conductive layer 210, Fig. 2A: while Challa’s device does not have a first diode string, the gate trench conductive layer 210 also represents the first diode string (in terms of the spatial arrangement), because gate trench conductive layer 210 corresponds to first semiconductor layer of Yilmaz, and the first diode string is a part (second part) of the first semiconductor layer in Yilmaz) by penetrating through the lightly doped region (drift region 206, Fig. 2A, [0113]) and the body doped region (body region 204, Fig. 2A, [0113]), the shielding structure (shield trenches 220, Fig. 2A) comprising a second semiconductor layer (conductive material 224, Fig. 2A, [0113]: “doped polysilicon”), wherein the second semiconductor layer (conductive material 224, Fig. 2A) comprises:
a fourth part (any part of the conductive material 224, Fig. 2A) having the first conductivity type (the same material as the gate material (gate trench conductive layer 210, Fig. 2A, [0113]), which has the first conductivity type (corresponding to the conductivity type of the first part of the first semiconductor layer in Yilmaz), Fig. 2A, [0113] and the cited reference Sapp (US 6,710,403 B2, col. 2, lines 35-37) in [0113]) and being connected to the source doped region (n+ source region 212, Fig. 2A, [0113]) through the first connection structure (metal layer 216, Fig. 2A, [0113]: “A metal layer 216 electrically connects conductive material 224 inside trenches 220 with the n+ source regions 212 and p+ heavy body regions 218”);
wherein in the first direction (vertical direction in Fig. 2A), a depth of the shielding structure (shield trenches 220, Fig. 2A) is greater than the first depth (the depth of the gate trench 202, Fig. 2A).
Challa further discloses that “The impact of deeper source shield trenches 220 is to push the depletion layer formed as a result of the reverse-biased body-drain junction deeper into drift region 206. Thus, a wider depletion region can result without increasing the electric field. This allows the drift region to be more highly doped without lowering the breakdown voltage. A more highly doped drift region reduces the transistor on-resistance. Moreover, the reduced electric field near the body-drain junction allows the channel length to be substantially reduced which further reduces the on-resistance of the transistor and substantially reduces the gate-to-source capacitance Cgs”. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include shielding structures, as taught by Challa, in the trench-type semiconductor power device of Yilmaz to obtain a device with reduced on-resistance and gate-to-source capacitance, which improves the device performance and features, including the speed, the breakdown voltage, and the heating. Thus, the combination of Yilmaz and Challa meets all the limitations of claim 9.
Regarding claim 11, Yilmaz and Challa teach the trench-type semiconductor power device of claim 9, wherein
Yilmaz teaches that the trench-type semiconductor power device of claim 9 further comprises:
an electrostatic discharge protection structure (the structure labeled as ESD structure in Illustrative Fig. 1, which is identical in structure to the first diode string, [0056])) located above or in a same horizontal plane (Illustrative Fig. 1: same horizontal plane) as the first semiconductor layer (first semiconductor layer, Illustrative Fig. 1), wherein the electrostatic discharge protection structure (ESD structure, Illustrative Fig. 1) comprises:
a third semiconductor layer (second semiconductor layer, Illustrative Fig. 1) comprising a plurality of fifth doped regions (N-type polysilicon layers 135-N in second semiconductor layer, Illustrative Fig. 1) having the first conductivity type (N-type) and a plurality of sixth doped regions (P-type polysilicon layers 135-P in second semiconductor layer, Illustrative Fig. 1) having the second conductivity type (P-type), wherein the plurality of fifth doped regions (N-type polysilicon layers 135-N in second semiconductor layer, Illustrative Fig. 1) and the plurality of sixth doped regions (P-type polysilicon layers 135-P in second semiconductor layer, Illustrative Fig. 1) are staggered to form a third diode string (shown as second diode string as shown in Illustrative Fig. 1) having one or more back-to-back diodes (Illustrative Fig. 1: second diode string comprises back-to-back diodes);
wherein a first end of the third diode string (bottom end of the second diode string in Illustrative Fig. 1) is electrically connected to the first end of the first diode string (first end, Illustrative Fig. 1), and a second end of the third diode string (top end of the second diode string in Illustrative Fig. 1) is electrically connected to the source doped region ([0056]-[0057]: connected to source (S) (Illustrative Fig. 1), and therefore connected to source doped region).
Allowable Subject Matter
Claims 10 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 10, claim 10 reciting the limitation that “the second semiconductor layer further comprises a fifth part distant from the source doped region and comprising a plurality of third doped regions having the first conductivity type and a plurality of fourth doped regions having the second conductivity type” would be allowable if this limitation is incorporated in a claim combining claim 1, claim 9, and all the remaining limitations of 10.
Regarding the closest prior art, as detailed above in claim rejection 9, Yilmaz in view of Challa teaches all the limitations of claim 9, but fails to teach the limitation above, and therefore the remaining limitations of claim 10, which further describe the third and fourth doped regions. There has been no prior art identified that can motivate the modification of the trench-type semiconductor power device of Yilmaz in view of Challa to include a plurality of third doped regions having the first conductivity type and a plurality of fourth doped regions having the second conductivity type in the second semiconductor layer. Accordingly, claim 10 is not anticipated or made obvious by any prior art identified. Therefore, claim 10 is objected.
Regarding claims 12, claim 12 reciting the limitation that “the shielding structure is disposed between the electrostatic discharge protection structure and the first diode string” would be allowable if this limitation is incorporated in a claim combining claim 1, claim 9, and claim 11.
Regarding the closest prior art, as detailed above in claim rejection 11, Yilmaz and Challa teach the trench-type semiconductor power device of claim 11, wherein
the combination of Yilmaz and Challa further teaches that the shielding structure (shield trenches 220 of Challa (Fig. 2A) incorporated with the trench-type semiconductor power device of Yilmaz (Figs. 11A-B) according claims 9 and 11) is separated from the electrostatic discharge protection structure (the structure labeled as ESD structure in Illustrative Fig. 1: Challa’s shielding structure surrounds the ESD structure and first semiconductor layer to provide shielding for the whole transistor).
The combination of Yilmaz and Challa, however, fails to teach that the shielding structure is disposed between the electrostatic discharge protection structure and the first diode string, because, in Yilmaz in view of Challa, the two neighboring trenches (one including the ESD structure, and the other the first diode string) are structures identical to each other, including also connected gate structures. Therefore, the two trenches together form the complete trench-type semiconductor power device. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would locate the shielding structure around these two trenches, not in between them. There has been no prior art identified that can motivate the modification of the trench-type semiconductor power device of Yilmaz in view of Challa to place the shielding structure between the electrostatic discharge protection structure and the first diode string. Accordingly, claim 12 is not anticipated or made obvious by any prior art identified, and therefore, claim 12 is objected.
Regarding claims 13, claim 13 reciting the limitation that “the shielding structure is disposed between the electrostatic discharge protection structure and the first diode string” would be allowable if this limitation is incorporated in a claim combining claim 1, claim 9, and claim 11.
Regarding the closest prior art, as detailed above in claim rejection 11, Yilmaz and Challa teach the trench-type semiconductor power device of claim 11, wherein
the combination of Yilmaz and Challa further teaches that the second semiconductor layer (conductive material 224 of Challa, Fig. 2A) of the shielding structure (shield trenches 220 of Challa (Fig. 2A) incorporated with the trench-type semiconductor power device of Yilmaz (Figs. 11A-B) according claims 9 and 11) abuts against the third semiconductor layer (second semiconductor layer in Illustrative Fig. 1) of the electrostatic discharge protection structure (the structure labeled as ESD structure in Illustrative Fig. 1: Challa’s shielding structure surrounds the ESD structure and first semiconductor layer to provide shielding for the whole transistor, and therefore one component of the shielding structure is at the left side of the ESD structure).
The combination of Yilmaz and Challa, however, fails to teach that the shielding structure is disposed between the electrostatic discharge protection structure and the first diode string, because, in Yilmaz in view of Challa, the two neighboring trenches (one including the ESD structure, and the other the first diode string) are structures identical to each other, including also connected gate structures. Therefore, the two trenches together form the complete trench-type semiconductor power device. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would locate the shielding structure around these two trenches, not in between them. There has been no prior art identified that can motivate the modification of the trench-type semiconductor power device of Yilmaz in view of Challa to place the shielding structure between the electrostatic discharge protection structure and the first diode string. Accordingly, claim 13 is not anticipated or made obvious by any prior art identified, and therefore, claim 13 is objected.
Regarding claims 14-20, claim 14 disclosing the limitations that “a fifth part … not overlapping the first semiconductor layer in the first direction”, would be allowable if this limitation is incorporated in a claim combining claim 1 and all the remaining limitations of claim 14.
Regarding relevant prior art, Yilmaz (US 2016/0260814 A1) and Challa (US 2006/0214222 A1) is identified as the closest prior art. Accordingly, Yilmaz teaches the trench-type semiconductor power device of claim 1, wherein Yilmaz also teaches that the trench structure (trench structure, Illustrative Fig. 1) further comprises,
a third semiconductor layer (first polysilicon layer 125 under the first semiconductor layer, Illustrative Fig. 1, [0039]) located between the first semiconductor layer (first semiconductor layer, Illustrative Fig. 1) and the lightly doped region (N-type epitaxial layer 110, Fig. 11A), wherein the third semiconductor layer (first polysilicon layer 125 under the first semiconductor layer, Illustrative Fig. 1) comprises:
a fourth part (part of the first polysilicon layer 125 under the first part of the first part of the first silicon layer, Illustrative Fig. 1) overlapping the first semiconductor layer (first silicon layer, Illustrative Fig. 1) in the first direction (first direction, Illustrative Fig. 1); and
a fifth part (part of the first polysilicon layer 125 under the first diode string, Illustrative Fig. 1) adjacent to the first diode string (first diode string, Illustrative Fig. 1: fifth part is adjacent to the bottom surface of the first diode string);
wherein the first semiconductor layer (first semiconductor layer, Illustrative Fig. 1) is separated from the third semiconductor layer (first polysilicon layer 125 under the first semiconductor layer, Illustrative Fig. 1) by penetrating through an insulating layer (inter-poly dielectric (IPD) layer 130, Illustrative Fig. 1).
Yilmaz, however, does not teach
the trench-type semiconductor device further comprising a shielding structure comprising a second semiconductor layer having the first conductivity type;
the fourth part having the first conductivity type;
the fifth part not overlapping the first semiconductor layer in the first direction; and
the shielding structure is adjacent to the fifth part of the third semiconductor layer and separated from the trench structure by penetrating through the lightly doped region and the body doped region.
Challa, on the other hand, teaches a trench-type semiconductor power device (dual trench power MOSFET 200, Fig. 2A, [0113]) with a first semiconductor layer (gate trench conductive layer 210, Fig. 2A, [0114]; “doped polysilicon” ([0109]) in a trench structure (gate trench 202, Fig. 2A, [0115]) as a gate (gate G, Fig. 2A), wherein the trench-type semiconductor power device also comprises a lightly doped region (drift region 206, Fig. 2A, [0114]) and a body doped region (body region, 204, Fig. 2A, [0113]). Challa further teaches that
the trench-type semiconductor power device comprises a shielding structure (shield trenches 220, Fig. 2A, [0113]) comprising a second semiconductor layer (conductive material 224, Fig. 2A, [0113]: “doped polysilicon”) having the first conductivity type (the same material as the gate material (gate trench conductive layer 210, Fig. 2A, [0113]), which has the first conductivity type (corresponding to the conductivity type of the first part of the first semiconductor layer in Yilmaz), Fig. 2A, [0113] and cited reference Sapp (US 6,710,403 B2, col. 2, lines 35-37));
the fourth part (first half of the conductive material 224 along the second direction, which is in to the page in Fig. 2A) having the first conductivity type (the same type as the conductive material 224); and
the shielding structure (shield trenches 220, Fig. 2A) is separated from the trench structure (gate trench 202, Fig. 2A) by penetrating through the lightly doped region (drift region 206, Fig. 2A) and the body doped region (body region, 204, Fig. 2A).
Challa further discloses that “The impact of deeper source shield trenches 220 is to push the depletion layer formed as a result of the reverse-biased body-drain junction deeper into drift region 206. Thus, a wider depletion region can result without increasing the electric field. This allows the drift region to be more highly doped without lowering the breakdown voltage. A more highly doped drift region reduces the transistor on-resistance. Moreover, the reduced electric field near the body-drain junction allows the channel length to be substantially reduced which further reduces the on-resistance of the transistor and substantially reduces the gate-to-source capacitance Cgs”. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include shielding structures, as taught by Challa, in the trench-type semiconductor power device of Yilmaz to obtain a device with reduced on-resistance and gate-to-source capacitance, which improves the device performance and features, including the speed, the breakdown voltage, and the heating. Thus, the combination of Yilmaz and Challa meets the limitations that
the trench-type semiconductor device further comprising a shielding structure comprising a second semiconductor layer having the first conductivity type;
the fourth part having the first conductivity type;
the shielding structure is adjacent to the fifth part of the third semiconductor layer (because the fifth part in Yilmaz is below the first semiconductor layer, and therefore adjacent to the shielding structure) and separated from the trench structure by penetrating through the lightly doped region and the body doped region.
The combination of Yilmaz and Challa, however, fails to teach
the fifth part not overlapping the first semiconductor layer in the first direction.
There has been no prior art identified that can further motivate the modification of the fifth part in the trench-type semiconductor power device of Yilmaz in view of Challa to make the fifth part not overlapping the first semiconductor layer in the first direction. In Yilmaz in view of Challa, the fifth part is below the first semiconductor layer, and there is no motivation to change this structure or arrangement to meet the limitation above. Accordingly, claim 14 is not anticipated or rendered obvious by any prior art identified. Therefore, claim 14 is objected.
Claims 15-20 are also objected to due to their direct or indirect dependency on claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsieh (2010/0289073 A1) teaches a trench MOSFET with an electrostatic discharge protection structure comprising back-to-back diodes, which is relevant to all claims.
Hsieh (US 2013/0092976 A1) teaches a trench MOSFET with an electrostatic discharge protection structure comprising back-to-back diodes, which is relevant to all claims.
Ku (US 2017/0018619 A1) teaches a trench MOSFET with a trench-type shielding structure, which is relevant to claims 9-20.
The Examiner further notes that another embodiment of Yilmaz (illustrated in Figs. 12A-B) also teaches claims 1-9, and 11, when combined with prior art of this office action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ILKER NMN OZDEN/Examiner, Art Unit 2812
/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
Prosecution Insights