DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 8-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PENG (US 20170104061).
Regarding claim 1, PENG discloses a method, comprising:
forming a first fin stack (fin 310a, see fig 3, para 28) and a second fin stack (fin 310b, see fig 3, para 28), including forming an oxide layer (206a can be an oxide layer, see fig 3, para 21) over nanostructures of the first fin stack and the second fin stack (310a and 310b comprise nanostructures 102 of alternating layers 102a and 102b, see fig 3, para 18);
forming a first liner layer (fig 4, 414a, para 28) over the first fin stack and the second fin stack;
forming a second liner layer (fig 4, 414b, para 29) over the first liner layer;
forming an isolation layer (412 is deposited over 310 after the liners 414, see fig 3-4, para 30) over the second liner layer; and
forming an isolation region by recessing the isolation layer while the oxide layer is covered by the second liner layer (portions of 412 extending over 310 which includes oxide 206a is done by CMP while 414b is present, see fig 3, para 30).
Regarding claim 2, PENG discloses the method of claim 1, further comprising:
exposing the first and second fin stacks by recessing the first and second liner layers (310a and 310b are exposed by removing parts of 414a and 414b, see fig 5, para 31);
forming an inactive fin structure (1136 have fin-shaped structures, see fig 11, para 42) over the isolation region; and
forming a gate structure (gate electrode 2470 and insulator 2468, see fig 24, para 62) over the first and second fin stacks and the inactive fin structure (2470 extends higher than 310 and 1136, see fig 24).
Regarding claim 3, PENG discloses the method of claim 2, further comprising:
forming a gate isolation feature over the inactive fin structure prior to the forming the gate structure (1140 is formed over 1136 before 2470, see fig 11, para 45).
Regarding claim 4, PENG discloses the method of claim 1, wherein the forming the isolation layer includes forming the isolation layer having different etch selectivity than the second liner layer (412 can be SiO, which has different etch selectivity than the SiN of 414b, see fig 4, para 29-30).
Regarding claim 5, PENG discloses the method of claim 4, wherein the forming the isolation layer includes forming the isolation layer having substantially the same material composition as the oxide layer (206a and 412 can both be silicon oxide, see fig 4, para 21 and 30).
Regarding claim 8, PENG discloses a method, comprising:
forming a multi-layer stack (FIG 1, 102, para 18) on a substrate (substrate 100, see fig 1, para 16) comprising alternating layers of first semiconductor layers (fig 1, 102a, para 18) and second semiconductor layers (fig 1, 102b, para 18);
patterning the multi-layer stack (the patterning in fig 3, see para 27) to define fins (the fins of 100 below each 102, see fig 3) and corresponding nanostructures (the remaining fin-shaped portions of 102, see fig 3, para 27);
depositing a first liner layer (fig 4, 414a, para 28) over the substrate, the fins, and the nanostructures;
depositing a second liner layer (fig 4, 414b, para 29) over the first liner layer;
forming an isolation layer (fig 4, 412, para 29-30) by depositing an insulative material (the insulating material of 412, see para 30) between the fins and nanostructures;
recessing the insulative material to define precise isolation regions (recessing 412 in fig 5, see para 31);
Regarding claim 9, PENG discloses the method of claim 8, wherein the second liner layer is formed of a material having different etch selectivity than the first liner layer (first liner layer 414a can be SiO and second liner layer 414b can be SiN, which can have different etch selectivity, see fig 4, para 29).
Regarding claim 10, PENG discloses the method of claim 8, wherein the recessing of the insulative material involves an etching process that is selective to the material of the insulative material (412 can be etched using 414 as an etch mask, so the etch must be selective to 414, see fig 5, para 31).
Regarding claim 11, PENG discloses the method of claim 8, further comprising:
forming dummy gate structures (fig 7, 720, para 36) over the fins and nanostructures;
removing portions of the first and second liner layers to expose underlying structures (the recessing of 414a and 414b in fig 5, see para 31); and
forming inactive fin structures (the fin-shaped structures formed over 720 comprising 622a, 622b and 826, see fig 8A, para 37) including liner layers (the plurality of layers in 826, see fig 8A, para 37) and fill layers (622a and 622b at least partially fill 826, see fig 8A) over the dummy gate structures (622a, 622b and 826 are over 720, see fig 7-8A).
Regarding claim 12, PENG discloses the method of claim 11, wherein the dummy gate structures are formed from amorphous silicon, polycrystalline silicon (620 which is formed into 720 can be poly Si, see fig 7, para 35), or metal nitride.
Regarding claim 13, PENG discloses the method of claim 11, further comprising:
replacing the dummy gate structures with replacement gate structures (720 is replaced with gate electrode 2470 and gate dielectric 2468, see fig 22-24, para 57-62) comprising work function metals (2470 can comprise TiN or WN, which are work function materials as described in the applicant's specification paragraph 23, see para 62) and high-k dielectrics (2468 can comprise one or more high-k dielectrics, see fig 24, para 61);
forming source/drain regions adjacent to the fins (source/drain regions 930, see fig 10, para 39); and
adding interlayer dielectrics (ILD layers 1136 and 2570, see fig 11 and 25, para 44 and 63) and source/drain contacts (fig 26, 2572, para 63).
Regarding claim 14, PENG discloses the method of claim 13, wherein the replacing of the dummy gate structures includes removing the dummy gate structures and forming the replacement gate structures by atomic layer deposition (ALD) (720 is removed, and 2468 can be formed by ALD, see para 56 and 61).
Regarding claim 15, PENG discloses the method of claim 13, further comprising:
forming gate spacers around the replacement gate structures using a material including silicon nitride, silicon oxynitride, or silicon carbide (fig 11, 1138, para 43).
Regarding claim 16, PENG discloses a method, comprising:
forming a multi-layer stack (FIG 1, 102, para 18) on a substrate (substrate 100, see fig 1, para 16) comprising alternating layers of first semiconductor layers (fig 1, 102a, para 18) and second semiconductor layers (fig 1, 102b, para 18);
patterning the multi-layer stack (the patterning in fig 3, see para 27) to define fins (the fins of 100 below each 102, see fig 3) and corresponding nanostructures (the remaining fin-shaped portions of 102, see fig 3, para 27);
depositing a first liner layer (fig 4, 414a, para 28) over the substrate, the fins, and the nanostructures;
depositing a second liner layer (fig 4, 414b, para 29) over the first liner layer;
forming an isolation layer (fig 4, 412, para 29-30) by depositing an insulative material (the insulating material of 412, see para 30) between the fins and nanostructures;
recessing the insulative material to define precise isolation regions (recessing 412 in fig 5, see para 31);
forming dummy gate structures (fig 7, 720, para 36) over the fins and nanostructures;
removing portions of the first and second liner layers to expose underlying structures (the recessing of 414a and 414b in fig 5, see para 31);
forming inactive fin structures (the fin-shaped structures formed over 720 comprising 622a, 622b and 826, see fig 8A, para 37) including liner layers (the plurality of layers in 826, see fig 8A, para 37) and fill layers (622a and 622b at least partially fill 826, see fig 8A) over the dummy gate structures (622a, 622b and 826 are over 720, see fig 7-8A);
replacing the dummy gate structures with replacement gate structures (720 is replaced with gate electrode 2470 and gate dielectric 2468, see fig 22-24, para 57-62) comprising work function metals (2470 can comprise TiN or WN, which are work function materials as described in the applicant's specification paragraph 23, see para 62) and high-k dielectrics (2468 can comprise one or more high-k dielectrics, see fig 24, para 61);
forming source/drain regions adjacent to the fins (source/drain regions 930, see fig 10, para 39); and
adding interlayer dielectrics (ILD layers 1136 and 2570, see fig 11 and 25, para 44 and 63) and source/drain contacts (fig 26, 2572, para 63).
Regarding claim 17, PENG discloses the method of claim 16, wherein the first and second liner layers are formed of materials having different etch selectivities (first liner layer 414a can be SiO and second liner layer 414b can be SiN, which can have different etch selectivity, see fig 4, para 29) to facilitate selective removal during the patterning process.
Regarding claim 18, PENG discloses The method of claim 16, wherein the forming the isolation layer includes forming the isolation layer having different etch selectivity than the second liner layer (412 can be SiO, which has a different etch selectivity than the SiN of the second liner layer 414b, see fig 4, para 29-30).
Regarding claim 19, PENG discloses the method of claim 16, wherein the forming the isolation layer includes forming the isolation layer having substantially the same material composition as an oxide layer is covered by the second liner layer (isolation layer 412 can be an oxide layer, see para 30, and has its bottom and side surfaces covered by 414b, see fig 4).
Regarding claim 20, PENG discloses the method of claim 16, wherein the recessing of the insulative material involves an etching process that is selective to the material of the insulative material (412 can be etched using 414 as an etch mask, so the etch must be selective to 414, see fig 5, para 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over PENG (US 20170104061) in view of CHING (US 20190165127).
Regarding claim 6, PENG discloses the method of claim 1.
PENG fails to explicitly disclose a method, further comprising: removing portions of the first liner layer by cutting the first and second fin stacks.
CHING teaches a method, further comprising: removing portions of the first liner layer by cutting the first and second fin stacks (a portion of first liner A1 is removed with portions of the fins 1500 and 1600, see fig 4, para 30).
PENG and CHING are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of PENG with the cutting of CHING because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of PENG with the cutting of CHING in order to prevent the loss of dummy fins during etching (see CHING para 24).
Regarding claim 7, PENG and CHING disclose the method of claim 6.
PENG fails to explicitly disclose a method, wherein portions of the second liner layer are formed in openings resulting from the removing the portions of the first liner layer.
CHING teaches a method, wherein portions of the second liner layer are formed in openings resulting from the removing the portions of the first liner layer (second liner layer A2 is formed in the cuts which removed A1, see fig 5, para 30).
PENG and CHING are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of PENG with the cutting of CHING because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of PENG with the cutting of CHING in order to prevent the loss of dummy fins during etching (see CHING para 24).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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