DETAILED ACTION
Information Disclosure Statement
The references cited within the IDS document (dated July 29, 2024) have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-9, 11, 12, 14, 15, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mochizuki et al. (US 2018/0358435 A1, hereinafter referred to as ‘Mochizuki’).
As to claim 1, Mochizuki teaches a semiconductor device, comprising:
semiconductor channel members (14A-C) vertically stacked over a substrate (10);
a gate stack (36/38) wrapping around the semiconductor channel members;
a gate spacer (20) disposed on sidewalls of the gate stack;
a source/drain (S/D) epitaxial feature (30) in contact with the semiconductor channel members; and
an insulating layer (24P) interposing the S/D epitaxial feature and the gate stack, wherein the insulating layer, the S/D epitaxial feature, and the gate spacer collectively define air gaps (32) stacked between adjacent ones of the semiconductor channel members. See figure 10.
As to claim 2, Mochizuki teaches a dielectric constant of the insulating layer is higher than a dielectric constant of the gate spacer. See paragraphs (0035) and (0043).
As to claim 3, Mochizuki teaches the dielectric constant of the insulating layer is about 1.5 times to about 3 times of the dielectric constant of the gate spacer. See paragraphs (0035) and (0043).
As to claim 5, Mochizuki teaches a portion of the S/D epitaxial feature interfacing the air gaps has a concave surface bending away from the gate stack. See figure 10.
As to claim 7, Mochizuki teaches in a cross-sectional view along a lengthwise direction of the semiconductor channel members, at least one of the air gaps has a dome shape. See figure 10.
As to claim 8, Mochizuki teaches in a cross-sectional view along a lengthwise direction of the semiconductor channel members, at least one of the air gaps has a triangular shape. See figure 10.
As to claim 9, Mochizuki teaches a surface of the semiconductor channel members in contact with the insulating layer has a (111) crystalline plane. See paragraph (0056).
As to claim 11, Mochizuki teaches a semiconductor device, comprising:
semiconductor channel members (14A-C) vertically stacked over a substrate;
a gate stack (36/38) wrapping around the semiconductor channel members;
a gate spacer (20) disposed on sidewalls of the gate stack;
an epitaxial feature (30) abutting the semiconductor channel members; and
an inner spacer interposing the epitaxial feature and the gate stack, wherein the inner spacer includes an air gap (32) and an insulating layer (24P) separating the air gap from the gate stack,
wherein in a first cross-sectional view along a lengthwise direction of the semiconductor channel members (14A-C) the air gap (32) is laterally bounded by the epitaxial feature (30) and the insulating layer (24P), and in a second cross-sectional view perpendicular to the lengthwise direction of the semiconductor channel members (14A-C) the air gap (32) is laterally bounded by the gate spacer (20). See figure 10.
As to claim 12, Mochizuki teaches a dielectric constant of the insulating layer (24P) ranges from about 5 to about 8. Insulating layer can be silicon nitride (see paragraph 0043) which as a known k value of ~6 to ~9.5.
As to claim 14, Mochizuki teaches the insulating layer is substantially free of oxygen (i.e. the insulating layer is silicon nitride, paragraph 0043).
As to claim 15, Mochizuki teaches the insulating layer includes a metal oxide. See paragraph (0043).
As to claim 17, Mochizuki teaches a semiconductor device, comprising:
semiconductor channel members (14A-C) vertically stacked over a substrate;
a gate stack (36/38) wrapping around the semiconductor channel members;
a gate spacer (20) disposed on sidewalls of the gate stack;
a source/drain (S/D) epitaxial feature (30) in contact with the semiconductor channel members; and
an inner spacer interposing the S/D epitaxial feature and the gate stack and stacked between adjacent two of the semiconductor channel members,
wherein the inner spacer includes an air gap (32) and an insulating layer (24P) separating the air gap from the gate stack and the adjacent two of the semiconductor channel members, the air gap exposes a sidewall of the S/D epitaxial feature, and a dielectric constant of the insulating layer is higher than a dielectric constant of the gate spacer (see paragraphs (0035) and (0043)).
As to claim 19, Mochizuki teaches the sidewall of the S/D epitaxial feature exposed in the air gap bends in a direction away from the gate stack. See figure 10.
Allowable Subject Matter
Claims 4, 6, 10, 13, 16, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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