DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 6, 11, 15 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 6, 11 and 15 recites “from about 0.4 to about 0.95”. Claims recites “substantially equal”.
The TERM ‘About’
The term "about" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “About” is defined as " almost or nearly—used to indicate that a number, amount, time, etc., is not exact or certain” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from + or - 0.4 or + or - 0.95 in order to be considered “about”. Examiner notes the 0.36, 0.37, 0.38 and 0.39 are all about 0.4 and the same is true for 0.96, 0.97 and 0.98 even though they are outside of claimed range. The term “about” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target anymore. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is 0.4 and 0.95) and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 18 inherits these deficiencies due to its dependency.
The TERM ‘Substantially’
The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from the height of the second conductive bump. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target anymore. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the height of the second conductive bump ), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation “the fourth conductive pillar” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner has taken this to be “the second conductive pillar” Claims 15-20 inherits these deficiencies due to their dependency. Appropriate correction is required.
EXAMINER’S COMMENTS
Examiner suggests that the Applicant review the current claims and/or possible amendments to claims to ensure that there are no further antecedent basis issues. The Applicant should also make spelling corrections in regards to the terms “forth” and “potion”, which should be “fourth” and “portion” and have been taken as such for the purpose of examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over FANG (US 2021/0366864 A1) in view of LIN et al. (LIN) (US 2020/0350277 A1).
In regards to claim 1, Fang (Fig. 1A-4B, 10A-13 and associated text) discloses a method of forming a semiconductor package (items 1, 1’, 1a, 1b, 1b’, 1c, 1d, 1e, 12H) comprising: alternately forming a plurality of dielectric layers (items 211-215) and a plurality of conductive layers (items 221-224) over a carrier (item 5); forming a first conductive bump (items 113 plus 114 or 114 plus 112) and a second conductive bump (items 123 plus 124 or 124 plus 122) on the dielectric layer (item 211) farthest away the carrier (item 5) and the conductive layer (item 221) farthest away the carrier (item 5), wherein each of the first conductive bump (items 113 plus 114 or 114 plus 112) and the second conductive bump (items 123 plus 124 or 124 plus 122) comprises a conductive pillar (items 114, 124) and a conductive cap (items 112, 122) on the conductive pillar (items 114, 124), providing a semiconductor device (items 3 or 3B) with a third conductive bump (items 111 or 111 plus 112) and a fourth conductive bump (items 121 or 121 plus 122), but does not specifically disclose a maximum lateral dimension of the conductive pillar of the first conductive bump is greater than a maximum lateral dimension of the conductive pillar of the second conductive bump, the conductive pillar of the first conductive bump comprises a main body portion and a peripheral portion wrapping the main body portion, the main body portion has a recess, and the conductive cap of the first conductive bump fills in the recess; providing a semiconductor device with a third conductive bump and a fourth conductive bump, wherein each of the third conductive bump and the fourth conductive bump comprises the conductive pillar and the conductive cap; and combining the conductive cap of the first conductive bump with the conductive cap of the third conductive bump to form a first joint structure and the conductive cap of the second conductive bump with the conductive cap of the fourth conductive bump to form a second joint structure.
LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 3A-3C, 3E and associated text) discloses that conductive pillars (items 311-316, 321-326) can have different widths (in regards to “a maximum lateral dimension of the conductive pillar of the first conductive bump is greater than a maximum lateral dimension of the conductive pillar of the second conductive bump”).
LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) also discloses the conductive pillar (items 320, 245 plus 250’ plus 252’ plus 260’, 311) of the first conductive bump (items 320, 321, 322, 323, 324, 325, 326) comprises a main body portion (middle portion with recess, Fig. 2A) and a peripheral portion (peripheral portion surrounding the recess, Fig. 2A) wrapping the main body portion (middle portion with recess, Fig. 2A), the main body portion has a recess (middle portion with recess, Fig. 2A), and the conductive cap (items 250’ plus 252’ plus 260’) of the first conductive bump (items 321, 322, 323, 324, 325, 326) fills in the recess; providing a semiconductor device (item 310) with a third conductive bump (items 300, 311, 312, 313, 314, 315 or 316) and a fourth conductive bump (items 300, 311, 312, 313, 314, 315 or 316), wherein each of the third conductive bump (items 300, 311, 312, 313, 314, 315 or 316) and the fourth conductive bump (items 300, 311, 312, 313, 314, 315 or 316) comprises the (a) conductive pillar (items 245 plus 250’ plus 252’) and the (a) conductive cap (item 260’); and combining the conductive cap (items 250’ plus 252’ plus 260’) of the first conductive bump (items 320, 321, 322, 323, 324, 325, 326) with the conductive cap (item 260’) of the third conductive bump (items 300, 311, 312, 313, 314, 315 or 316) to form a first joint structure (items 331, 332, 333, 334, 335 or 336) and the conductive cap (item 260’) of the second conductive bump (items 320, 321, 322, 323, 324, 325, 326) with the conductive cap (item 260’) of the fourth conductive bump (items 300, 311, 312, 313, 314, 315 or 316) to form a second joint structure (items 331, 332, 333, 334, 335 or 336).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of LIN for the purpose of enabling bumps toe have equal bump heights (paragraph 43) and current flow/density.
It would have been obvious to modify the invention to include a maximum lateral dimension of the conductive pillar of the first conductive bump being greater than a maximum lateral dimension of the conductive pillar of the second conductive bump, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 2, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by Lin discloses wherein the main body portion comprises a first portion (via portion of item 114) embedded in the dielectric layer (item 211) farthest away the carrier and a second portion (portion of item 114 over via portion of item 114) over the first portion (via portion of item 114), the conductive pillar (item 123 plus 124) of the second conductive bump (item 123 plus 124) comprises a third portion (via portion of item 124) embedded in the dielectric layer farthest away the carrier and a fourth portion (portion of item 124 over via portion of item 124) over the third portion (via portion of item 124), and a maximum lateral dimension of the first portion is greater than a maximum lateral dimension of the third portion (different widths as taught by Lin).
It would have been obvious to modify the invention to include a maximum lateral dimension of the first portion being greater than a maximum lateral dimension of the third portion, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 3, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) discloses wherein a height of the first conductive bump (items 320, 321, 322, 323, 324, 325, 326, LIN) is substantially equal to a height of the second conductive bump (items 320, 321, 322, 323, 324, 325, 326, LIN).
In regards to claim 4, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) discloses further comprising: forming an underfill layer (item 15, Fang, item 54, LIN) surrounding the first joint structure (items 11 or 12, Fang, items 331, 332, 333, 334, 335 or 336, LIN) and the second joint structure (items 11 or 12, Fang, items 331, 332, 333, 334, 335 or 336, LIN); and encapsulating the semiconductor device (items 3, 3B, Fang, item 310, 310’) and the underfill layer (item 15, Fang, item 54, LIN) by an encapsulant (item 13).
In regards to claim 5, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) discloses further comprising: aligning the first conductive bump (items 320, 321, 322, 323, 324, 325, 326, LIN) with the third conductive bump (items 300, 311, 312, 313, 314, 315 or 316, LIN) and the second conductive bump (items 320, 321, 322, 323, 324, 325, 326, LIN) with the fourth conductive bump (items 300, 311, 312, 313, 314, 315 or 316, LIN) before combining the conductive cap (items 250’ plus 252’ plus 260’, LIN) of the first conductive bump (items 320, 321, 322, 323, 324, 325, 326, LIN) with the conductive cap (item 260’, LIN) of the third conductive bump (items 300, 311, 312, 313, 314, 315 or 316, LIN) and the conductive cap (items 250’ plus 252’ plus 260’, LIN) of the second conductive bump (items 320, 321, 322, 323, 324, 325, 326, LIN) with the conductive cap (item 260’, LIN) of the fourth conductive bump (items 300, 311, 312, 313, 314, 315 or 316, LIN).
In regards to claim 6, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) does not specifically disclose wherein a ratio of a maximum lateral dimension of the main body portion to the maximum lateral dimension of the conductive pillar of the first conductive bump ranges from about 0.4 to 0.95.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ratio of a maximum lateral dimension of the main body portion to the maximum lateral dimension of the conductive pillar of the first conductive bump ranging from about 0.4 to 0.95, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 14, Fang (Fig. 1A-4B, 10A-13 and associated text) discloses a method of forming a semiconductor package, comprising: providing a semiconductor device (items 3, 3B) with a first conductive bump (item 111 plus 112) and a second conductive bump (item 121 plus 122), wherein the first conductive bump (item 111 plus 112) comprises a first conductive pillar (item 111) and a first conductive cap (item 112) on the first conductive pillar (item 111), and the second conductive bump (item 121 plus 122) comprises a second conductive pillar (item 121) and a second conductive cap (item 122) on the fourth (second) conductive pillar (item 121); providing a redistribution structure (item 2) below the semiconductor device (items 3, 3B) along a first direction, wherein the redistribution structure (item 2) comprises dielectric layers (items 211-215) sequentially stacked along the first direction; forming a third conductive bump (items 113 plus 114) and a fourth conductive bump (items 123 plus 124) on the dielectric layer (item 211) closest to the semiconductor device (items 3, 3B) and electrically connected with the redistribution structure (item 2), wherein the third conductive bump (items 113 plus 114) comprises a third conductive pillar (item 114), the fourth conductive bump (items 123 plus 124) comprises a fourth conductive pillar (item 124), each of the third conductive pillar (item 114) and the fourth conductive pillar (item 124) comprises a via portion (via portions of items 114 and 124) penetrating through the dielectric layer (item 211) closest to the semiconductor device (items 3, 3B) and a pillar portion (pillar portions of items 114 and 124) over the via portion (via portions of items 114 and 124), but does not specifically disclose wherein the third conductive bump comprises a third conductive pillar and a third conductive cap on the third conductive pillar, the fourth conductive bump comprises a fourth conductive pillar and a fourth conductive cap on the fourth conductive pillar…a maximum dimension of the via potion of the third conductive pillar along a second direction is greater than a maximum dimension of the via potion of the fourth conductive pillar along the second direction, a maximum dimension of the pillar potion of the third conductive pillar along the second direction is greater than a maximum dimension of the pillar potion of the fourth conductive pillar along the second direction, and the second direction is perpendicular to the first direction; and bonding the first conductive cap with the third conductive cap to form a first joint structure and the second conductive cap with the fourth conductive cap to form a second joint structure.
LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 3A-3C, 3E and associated text) discloses that conductive pillars (items 311-316, 321-326) can have different widths (in regards to “a maximum dimension of the via potion of the third conductive pillar along a second direction is greater than a maximum dimension of the via potion of the fourth conductive pillar along the second direction, a maximum dimension of the pillar potion of the third conductive pillar along the second direction is greater than a maximum dimension of the pillar potion of the fourth conductive pillar along the second direction, and the second direction is perpendicular to the first direction”).
LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) also discloses wherein the third conductive bump (items 320, 321, 322, 323, 324, 325, 326) comprises a third conductive pillar (items 245 or 245 plus 250’ plus 252’) and a third conductive cap (item 260’) on the third conductive pillar, the fourth conductive bump (items 320, 321, 322, 323, 324, 325, 326) comprises a fourth conductive pillar (items 245 or 245 plus 250’ plus 252’) and a fourth conductive cap (item 260’) on the fourth conductive pillar (items 245 plus 250’ plus 252’) …; and bonding the first conductive cap (item 260’) with the third conductive cap (item 260’) to form a first joint structure (items 331, 332, 333, 334, 335 or 336)and the second conductive cap (item 260’) with the fourth conductive cap (item 260’) to form a second joint structure (items 331, 332, 333, 334, 335 or 336).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of LIN for the purpose of enabling bumps toe have equal bump heights (paragraph 43) and current flow/density.
It would have been obvious to modify the invention to include a maximum dimension of the via potion of the third conductive pillar along a second direction being greater than a maximum dimension of the via potion of the fourth conductive pillar along the second direction, a maximum dimension of the pillar potion of the third conductive pillar along the second direction being greater than a maximum dimension of the pillar potion of the fourth conductive pillar along the second direction, and the second direction is perpendicular to the first direction, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 15, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) does not specifically disclose wherein a ratio of the maximum dimension of the via portion of the third conductive pillar along the second direction to the maximum dimension of the pillar portion of the third conductive pillar along the second direction ranges from about 0.4 to about 0.95.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ratio of the maximum dimension of the via portion of the third conductive pillar along the second direction to the maximum dimension of the pillar portion of the third conductive pillar along the second direction ranges from about 0.4 to about 0.95, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 16, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) discloses wherein the pillar potion of the third conductive pillar (pillar portions of items 114 and 124, pillar portion of items 245 or 245 plus 250’ plus 252’, LIN) comprises a recess (shown but not labeled in LIN) on a top surface thereof, and a vertical projection of the recess along the first direction overlaps with a span of the via portion (via portions of items 114 and 124, via portion of items 245 or 245 plus 250’ plus 252’, LIN) of the third conductive pillar (items 114 and 124, items 245 or 245 plus 250’ plus 252’, LIN).
In regards to claim 17, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) discloses wherein a depth of the recess is less than or equal to a height of the via portion of the third conductive pillar (items 114 and 124, items 245 or 245 plus 250’ plus 252’, LIN).
In regards to claim 18, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified wherein the redistribution structure (item 2) further comprises conductive layers (items 221-224), the conductive layers (items 221-224)and the dielectric layers (items 211-215) are stacked alternately along the first direction, and the third conductive pillar (items 113 plus 114) and the fourth conductive pillar (items 123 plus 124) are in contact with the conductive layer (item 221) closest to the semiconductor device (items 3, 3B).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over FANG (US 2021/0366864 A1) in view of LIN et al. (LIN) (US 2020/0350277 A1) in view of Kuo et al. (Kuo) (US 2011/0193220 A1) in view of Choi et al. (Choi) (US 2017/0358545 A1).
In regards to claim 19, Fang (Figs. 1B, 7 and associated text and items) as modified by LIN (Abstract, paragraph 58, 59, claim 1, Figs. 1, 3A-3B, 3E and associated text) and Kuo (Figs. 6, 7 and associated text) discloses wherein each of the first conductive pillar (items 114 or 124, FANG, items 321-326, Lin, items 410 or 410 plus 510 or 410 plus 510 plus 610, Kuo), the second conductive bump (pillar) (items 114 or 124, FANG, items 321-326, Lin, items 410 or 410 plus 510 or 410 plus 510 plus 610, Kuo), the third conductive bump (pillar) (items 114 or 124, FANG, items 321-326, Lin, items 410 or 410 plus 510 or 410 plus 510 plus 610, Kuo), and the fourth conductive bump (pillar) (items 114 or 124, FANG, items 321-326, Lin, items 410 or 410 plus 510 or 410 plus 510 plus 610, Kuo) comprises: a first copper-containing layer (item 410, paragraph 26, Kuo); a nickel-containing layer (item 510, paragraph 26, Kuo) overlying the first copper-containing (item 410, Kuo), and intermetallic compound (IMC) layer (item 612) overlying the nickel-containing layer (item 510), but does not specifically disclose a second copper-containing layer overlying the nickel-containing layer.
Choi (paragraph 43, Fig. 3 and associated text) discloses a first copper-containing layer (items 132 or 132 plus 134); a nickel-containing layer (item 136) overlying the first copper-containing (items 132 or 132 plus 134); and second copper-containing layer (item 138) overlying the nickel-containing layer (item 136).
It would have been obvious to modify the invention to include a first copper layer, nickel-containing layer and second copper-containing layer for the purpose of an electrical connection and bonding, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 20, Fang (Figs. 1B, 7 and associated text and items) as modified by LIN (Abstract, paragraph 58, 59, claim 1, Figs. 1, 3A-3B, 3E and associated text), Kuo (Figs. 6, 7 and associated text) and Choi (paragraph 43, Fig. 3 and associated text) discloses wherein the via portion (via portion items 410, 410 plus 510 or 410 plus 510 plus 612, Kuo) is formed by a portion of the first copper-containing layer (item 410), and the pillar portion (pillar portion of items 410 plus 510, Kuo, items 132 plus 134 plus 136 plus 138 Choi) is formed by the nickel-containing layer (item 510, Kuo, item 136, Choi), the second copper-containing layer (item 138, Choi) and another portion of the first copper-containing layer (item 410, Kuo, items 132 or 132 plus 134, Choi).
Claim(s) 7-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over FANG (US 2021/0366864 A1) in view of LIN et al. (LIN) (US 2020/0350277 A1) in view of Kuo et al. (Kuo) (US 2011/0193220 A1).
In regards to claim 7, Fang (Fig. 1A-4B, 10A-13 and associated text) discloses a method of forming a semiconductor package, comprising: forming a redistribution structure (item 2, paragraph 28) having a first surface and a second surface opposite to the first surface; forming a first conductive pillar (items 113 plus 114 or 114 plus 112) and a second conductive pillar (items 123 plus 124 or 124 plus 122) on the first surface of the redistribution structure (item 2) and electrically connected with the redistribution structure (item 2)…forming a first conductive cap (item 112) and a second conductive cap (item 122) respectively on the first conductive pillar (items 113 plus 114 or 114 plus 112) and the second conductive pillar (items 123 plus 124 or 124 plus 122), wherein the first conductive cap (item 112) is in contact with the top surface of the first conductive pillar (items 113 plus 114 or 114 plus 112), and the second conductive cap (item 122) is in contact with the top surface of the second conductive pillar (items 123 plus 124 or 124 plus 122), but does not specifically disclose wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar…providing a semiconductor device with a first conductive bump and a second conductive bump over the first surface of the redistribution structure, wherein the first conductive bump comprises a third conductive pillar and a third conductive cap on the third conductive pillar, and the second conductive bump comprises a fourth conductive pillar and a fourth conductive cap on the fourth conductive pillar; and bonding the first conductive cap with the third conductive cap to form a first joint structure and the second conductive cap with the fourth conductive cap to form a second joint structure.
LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 3A-3C, 3E and associated text) discloses that conductive pillars (items 311-316, 321-326) can have different widths (in regards to “a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar”).
LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) also discloses providing a semiconductor device (item 310) with a first conductive bump (items 300, 311, 312, 313, 314, 315 or 316) and a second conductive bump (items 300, 311, 312, 313, 314, 315 or 316) over the first surface of the redistribution structure (item 320), wherein the first conductive bump (items 300, 311, 312, 313, 314, 315 or 316) comprises a third conductive pillar (items 245 plus 250’ plus 252’) and a third conductive cap (item 260’) on the third conductive pillar (items 245 plus 250’ plus 252’), and the second conductive bump (items 300, 311, 312, 313, 314, 315 or 316) comprises a fourth conductive pillar (items 245 plus 250’ plus 252’) and a fourth conductive cap (item 260’) on the fourth conductive pillar (items 245 plus 250’ plus 252’); and bonding the first conductive cap (item 260’) with the third conductive cap (item 260’) to form a first joint structure (items 331, 332, 333, 334, 335 or 336) and the second conductive cap (item 260’) with the fourth conductive cap (item 260’) to form a second joint structure (items 331, 332, 333, 334, 335 or 336).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of LIN for the purpose of enabling bumps toe have equal bump heights (paragraph 43) and current flow/density.
It would have been obvious to modify the invention to include a maximum lateral dimension of the conductive pillar of the first conductive bump being greater than a maximum lateral dimension of the conductive pillar of the second conductive bump, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Fang as modified by LIN does not specifically disclose a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar;
Kuo (Figs. 6, 7 and associated text) discloses a topography variation of a top surface of a conductive pillar (items 410, 410 plus 510, 410 plus 510 plus 612).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kuo for the purpose of reducing crack propagation.
In regards to claim 8, LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) also discloses the conductive pillar (items 320, 245 plus 250’ plus 252’ plus 260’, 311) of the first conductive bump (items 320, 321, 322, 323, 324, 325, 326) comprises a main body portion (middle portion with recess, Fig. 2A) and a peripheral portion (peripheral portion surrounding the recess, Fig. 2A) wrapping the main body portion (middle portion with recess, Fig. 2A), the main body portion has a recess (middle portion with recess, Fig. 2A).
In regards to claim 9, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by Lin discloses wherein the main body portion comprises a first portion (via portion of item 114) embedded in the redistribution structure (item 2) farthest away the carrier and a second portion (portion of item 114 over via portion of item 114) over the first portion (via portion of item 114), the second conductive pillar (item 123 plus 124) comprises a third portion (via portion of item 124) embedded in the redistribution structure (item 2) and a fourth portion (portion of item 124 over via portion of item 124) over the third portion (via portion of item 124), and a maximum lateral dimension of the first portion is greater than a maximum lateral dimension of the third portion (different widths as taught by Lin).
It would have been obvious to modify the invention to include a maximum lateral dimension of the first portion being greater than a maximum lateral dimension of the third portion, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 10, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by Lin discloses wherein the recess (shown but not labeled, LIN) is located on the top surface of the first conductive pillar, and the first conductive cap (items 250’ plus 252’, LIN) fills in the recess.
In regards to claim 11, Fang as modified by LIN and Kuo does not specifically disclose wherein a ratio of a maximum lateral dimension of the main body portion to the maximum lateral dimension of the first conductive pillar ranges from about 0.4 to 0.95.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ratio of a maximum lateral dimension of the main body portion to the maximum lateral dimension of the conductive pillar of the first conductive bump ranging from about 0.4 to 0.95, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 12, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by Lin discloses wherein the step of forming the first conductive cap and the second conductive cap comprising performing a reflow process (paragraph 89, Fang).
In regards to claim 13, Fang (Fig. 1A-4B, 10A-13 and associated text) as modified by LIN (Abstract, paragraphs 58, 59, claim 1, Figs. 1, 2A, 3A-3C, 3E and associated text) also discloses comprising forming conductive terminals (item 522, Fang, item 15, Lin) over the second surface of the redistribution structure (item 2, Fang, item 30, LIN) to be electrically connected with the redistribution structure (item 2, Fang, item 30, LIN).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 October 5, 2026
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