DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites the limitation “at least one first fine (10b)” in line 2. However, the drawing reference number “(10b)” is unnecessary and should be deleted. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 and 10-17 of U.S. Patent No. 11,837,506. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 1-15 is similar to that of the claimed limitations of U.S. Patent No. 11,837,506 as claimed in claims 1-7 and 10-17 Therefore, the claims are not patentably distinct from each other.
The instant application:
1. A FinFET device, comprising: a substrate having at least one first fin and an isolation layer covering a lower portion of the at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode, wherein the first material layer and the second material layer are in contact with the isolation layer.
2. The FinFET device of claim 1, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer but separated from the first material layer.
8. The FinFET device of claim 1, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
3. The FinFET device of claim 1, wherein the second material layer has at least one tailing profile toward the isolation layer.
4. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
5. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
6. The FinFET device of claim 1, wherein the second material layer has a uniform germanium concentration within the at least one first fin above the isolation layer.
7. The FinFET device of claim 1, wherein the second material layer has a gradient germanium concentration within the at least one first fin above the isolation layer. 9. A FinFET device, comprising: a substrate having at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode, wherein the first material layer has a tapered top portion encapsulated by the second material layer.
10. The FinFET device of claim 9, further comprising an isolation layer covering a lower portion of the at least one first fin.
13. The FinFET device of claim 9, wherein the first material layer comprises a first semiconductor material, and the second material layer comprises a second semiconductor material different from the first semiconductor material.
14. The FinFET device of claim 9, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
15. The FinFET device of claim 9, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer.
11. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
12. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
US Patent No. 11,837,506:
1. A FinFET device, comprising: a substrate having at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the at least one first fin and the at least one second fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer, and an interface between the first material layer and the second material layer is uneven; a first gate strip disposed across the at least one first fin; and a second gate strip disposed across the at least one second fin, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
3. The FinFET device of claim 1, wherein the second material layer has two tailing portions in contact with the isolation layer.
2. The FinFET device of claim 1, wherein the second material layer has a tailing profile toward the isolation layer.
4. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
5. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer surrounding the first material layer.
6. The FinFET device of claim 1, wherein the second material layer has a uniform germanium concentration within the at least one first fin above the isolation layer.
7. The FinFET device of claim 1, wherein the second material layer has a gradient germanium concentration within the at least one first fin above the isolation layer.
10. A FinFET device, comprising: a substrate having at least one first fin and an isolation layer covering a lower portion of the at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and a first gate strip disposed across the at least one first fin, wherein the first gate strip is in physical contact with the second material layer but separated from the first material layer, and wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
11. The FinFET device of claim 10, wherein the second material layer has at least one tailing profile toward the isolation layer.
12. The FinFET device of claim 10, wherein the second material layer covers a sidewall and a top surface of the first material layer.
15. The FinFET device of claim 10, wherein the second material layer has a uniform germanium concentration within the at least one first fin above the isolation layer. 16. The FinFET device of claim 10, wherein the second material layer has a gradient germanium concentration within the at least one first fin above the isolation layer. 17. The FinFET device of claim 10, wherein the second material layer has two tailing portions in contact with the isolation layer.
13. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
14. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
Claims 1- 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1- 20 of U.S. Patent No. 12,148,673. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 1-20 is similar to that of the claimed limitations of U.S. Patent No. 12,148,673 as claimed in claims 1-20 Therefore, the claims are not patentably distinct from each other.
The instant application:
1. A FinFET device, comprising: a substrate having at least one first fin and an isolation layer covering a lower portion of the at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode, wherein the first material layer and the second material layer are in contact with the isolation layer.
2. The FinFET device of claim 1, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer but separated from the first material layer.
3. The FinFET device of claim 1, wherein the second material layer has at least one tailing profile toward the isolation layer.
4. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
5. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
6. The FinFET device of claim 1, wherein the second material layer has a uniform germanium concentration within the at least one first fin above the isolation layer.
7. The FinFET device of claim 1, wherein the second material layer has a gradient germanium concentration within the at least one first fin above the isolation layer. 8. The FinFET device of claim 1, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
9. A FinFET device, comprising: a substrate having at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode, wherein the first material layer has a tapered top portion encapsulated by the second material layer.
10. The FinFET device of claim 9, further comprising an isolation layer covering a lower portion of the at least one first fin.
11. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
12. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
13. The FinFET device of claim 9, wherein the first material layer comprises a first semiconductor material, and the second material layer comprises a second semiconductor material different from the first semiconductor material.
14. The FinFET device of claim 9, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
15. The FinFET device of claim 9, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer.
16. A method of forming a FinFET device, comprising: providing a substrate having at least one first fin, the first fin comprising a first material; forming a second material on a surface of the first fin; performing an annealing process to drive the second material into the first fin, so the second material is driven downwardly toward the substrate and the first material has a tapered top portion encapsulated by the second material after the annealing process; and forming a first gate strip across the first fin.
17. The method of claim 16, wherein an interface between the first material and the second material is uneven.
18. The method of claim 16, wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material is further driven toward the isolation layer during the annealing process. 19. The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material after the annealing process.
20. The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material layer and the first material layer after the annealing process.
US Patent No. 12,148,673:
1. A FinFET device, comprising: a substrate having at least one first fin and an isolation layer covering a lower portion of the at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer but separated from the first material layer.
2. The FinFET device of claim 1, wherein the second material layer has at least one tailing profile toward the isolation layer. 3. The FinFET device of claim 1, wherein the second material layer covers a sidewall and a top surface of the first material layer.
4. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
5. The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
6. The FinFET device of claim 1, wherein the second material layer has a uniform germanium concentration within the at least one first fin above the isolation layer.
7. The FinFET device of claim 1, wherein the second material layer has a gradient germanium concentration within the at least one first fin above the isolation layer.
8. The FinFET device of claim 1, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
9. A FinFET device, comprising: a substrate having at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer, and the second material layer has two tailing portions downwardly toward the substrate; and a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode.
10. The FinFET device of claim 9, further
comprising an isolation layer covering a lower portion of the at least one first fin.
11. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer.
12. The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.
13. The FinFET device of claim 9, wherein the first material layer comprises a first semiconductor material, and the second material layer comprises a second semiconductor material different from the first semiconductor material.
14. The FinFET device of claim 9, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.
15. The FinFET device of claim 9, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer.
16. A method of forming a FinFET device, comprising: providing a substrate having at least one first fin, the first fin comprising a first material; forming a second material on a surface of the first fin; performing an annealing process to drive the second material into the first fin, so the second material layer is tapered downwardly toward the substrate after the annealing process; and forming a first gate strip across the first fin.
17. The method of claim 16, wherein an interface between the first material and the second material is uneven.
18. The method of claim 16, wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material of the transforming layer is further driven toward the isolation layer.
19. The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material after the annealing process.
20. The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material layer and the first material layer after the annealing process.
Claims 16- 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4-7 of U.S. Patent No. 10,847,426. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 16-20 is similar to that of the claimed limitations of U.S. Patent No. 10,847,426 as claimed in claims 1 and 4-7 Therefore, the claims are not patentably distinct from each other.
The instant application:
16. A method of forming a FinFET device, comprising: providing a substrate having at least one first fin, the first fin comprising a first material; forming a second material on a surface of the first fin; performing an annealing process to drive the second material into the first fin, so the second material is driven downwardly toward the substrate and the first material has a tapered top portion encapsulated by the second material after the annealing process; and forming a first gate strip across the first fin.
17. The method of claim 16, wherein an interface between the first material and the second material is uneven.
18. The method of claim 16, wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material is further driven toward the isolation layer during the annealing process.
19. The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material after the annealing process.
20. The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material layer and the first material layer after the annealing process.
US Patent No. 10,847,426:
1. A method of forming a FinFET device, comprising: providing a substrate having at least one first fin, the first fin comprising a first material; performing a transforming process to the first fin to transform a portion of the first material into a second material, and an interface between the first material and the second material is uneven; and forming a first gate strip across the first fin. 4. The method of claim 1, wherein the transforming process comprises: forming a transforming layer comprising the second material on a surface of the first fin; and performing an annealing process to drive the second material into the first fin.
5. The method of claim 4, wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material of the transforming layer is further driven toward the isolation layer.
6. The method of claim 5, wherein the first material of the first fin above the isolation layer is completely transformed into the second material.
7. The method of claim 5, wherein the first material of the first fin above the isolation layer is partially transformed into the second material.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Cheng et al. (US 2018/0247938) disclose a FinFET device that includes plurality of FINs and isolation layer; a gate dielectric layer covers the FINs and and isolation layer and gate electrode formed over the gate electrode.
Correspondence
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
August 6, 2026
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