DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no. 2021/0367143 A1-cited in IDS) in view of Ahn (US Patent 10,497,858 B1-cited in IDS).
Regarding claim 1, Lee et al discloses a semiconductor device(fig. 5), comprising: a spin orbit torque (SOT) layer (SHE 10) on a substrate(102)[0065][0075];
a magnetic tunneling junction (MTJ) (100)on the SOT layer(10)[0076]; a hard mask (80)on the MTJ(100) [0077]; and a cap layer (210)on and directly contacting the SOT layer(SHE 10) and the hard mask(80), wherein the cap layer(210) directly on the SOT layer(SHE10) and the cap layer(210) on sidewalls of the MTJ(100) and a sidewall of the cap layer (210)is aligned with a sidewall of the SOT layer(SHE 10).
Lee et al fails to teach that the cap layer comprise different thicknesses.
However, Ahn et al discloses a non-conformal passivation layer comprising thickness variations among different locations of the passivation layer (422) corresponding to the MTJ-455 and SOT406(col. 10, lines 44-50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al with the teachings of Ahn et al in order to provide different degrees of protection to different locations of the substrate.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no. 2021/0367143 A1) in view of Ahn (US Patent 10,497,858 B1) as applied to claim 1 and further in view of Chuang (US Pub no. 2021/0098529 A1-cited in IDS).
Regarding claim 2, Lee et al as modified by Ahn et al discloses all the claim limitations and further teaches wherein the substrate comprises a magnetic random access memory (MRAM) region, the semiconductor device comprising: a first inter-metal dielectric (IMD) layer (104)on the substrate(102)[0058] fig. 5; a first metal interconnection (118)and a second metal interconnection(118) in the first IMD layer (104)on the MRAM region[0058]; the SOT layer (SHE10)on the first metal interconnection(118) and the second metal interconnection(118) fig. 5; the MTJ (100)on the SOT layer(SHE10) fig. 5; the hard mask (80)on the MTJ(100); a second IMD layer (210)around the MTJ(100)[0081] but fails to teach a logic region and a third metal interconnection in the second IMD layer on the logic region.
However, Chuang et al discloses a MRAM device with a logic region (10b)[0009]; and forming a third metal interconnection(158d) on the logic region(10b)[0038]. It would
have been obvious to one of ordinary skill in the art before the effective filing date of the
invention to modify Lee et al & Ahn et al with the teachings of Chuang et al to provide the use of core or I/O circuits.
Regarding claim 3, Lee et al as modified by Ahn et al discloses a stop layer [0089]on the second IMD layer(210)[0089] fig . 5 but fails to teach a third IMD layer on the stop layer; a fourth metal interconnection on the MRAM region to connect to the SOT layer; and a fifth metal interconnection on the logic region to connect to the third metal interconnection.
Chuang et al discloses a third IMD layer(166) on the stop layer(162); a fourth metal interconnection(189B) on the MRAM region (10a); and a fifth metal interconnection (188B)on the logic region(10b) to connect to the third metal interconnection(158B) fig. 27[0042-0044]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al & Ahn et al with the teachings of Chuang et al such that a stop layer on the second IMD layer; f a third IMD layer on the stop layer; a fourth metal interconnection on the MRAM region
to connect to the SOT layer; and a fifth metal interconnection on the logic region
to connect to the third metal interconnection results to provide an integrated circuit.
Regarding claim 4, Lee et al as modified by Ahn et al & Chuang et al discloses the limitations of claim 2, Chuang et al discloses wherein a top surface of a cap layer (136)is lower than a top surface of the third metal interconnection(158d) It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al & Ahn et al with the teachings of Chuang et al to prevent contamination.
Regarding claim 5, Lee et al as modified by Ahn et al discloses wherein a first portion of the cap layer (210)on the first IMD layer(124a/104) and a second portion of the cap layer(210) adjacent to the MTJ (100) fig. 5. Ahn et al discloses comprise different thicknesses (a non-conformal passivation layer comprising thickness variations among different locations of the passivation layer (422) corresponding to the MTJ-455 and SOT406) (col. 10, lines 44-50).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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