Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,154,867 B2 and US 11,791,291 B2 to Lu.
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the instant application.
For rejection purposes, the instant application will be rejected using parent patent US 12,154,867 B2, as an example.
Regarding independent claim 1: Lu teaches (e.g., Claims 1-12) a multiplexer cell, comprising:
a semiconductor substrate; a conductive layer, formed over the semiconductor substrate; and
a plurality of pairs of transistors, formed on the semiconductor substrate, each pair of transistors comprising a p-channel transistor and an n-channel transistor;
each of the p-channel transistor and the n-channel transistor comprising: a poly gate segment formed on the semiconductor substrate,
a first portion of the poly gate segment extending across an active region of the semiconductor substrate; a first contact element and
a second contact element, formed on a second portion of the poly gate segment and spaced apart from each other;
a first source/drain region and a second source/drain region, formed in the active region and located at opposite sides of the first portion of the poly gate segment; and
a third contact element and a fourth contact element, formed on the first source/drain region and the second source/drain region respectively,
wherein the first contact element and the second contact element are formed under and in contact with the conductive layer, and arranged along a first direction; the third contact element and the fourth contact element are formed under and in contact with the conductive layer, and arranged along the first direction;
at least one of the first contact element, the second contact element, the third contact element and the fourth contact element is electrically non-conductive (Claim 1).
Regarding claim 2: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the second portion of the poly gate segment extends outward from the opposite sides of the first portion of the poly gate segment (Claim 2).
Regarding claim 3: Lu teaches the claim limitation of the multiplexer cell of claim 2, on which this claim depends,
wherein the first contact element and the second contact element are formed on opposite ends of the second portion of the poly gate segment (Claim 2).
Regarding claim 4: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the first direction is perpendicular to a second direction along which the first portion of the poly gate segment extends (Claim 2).
Regarding claim 5: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the first contact element and the second contact element are in contact with a first conductive portion and a second conductive portion of the conductive layer, respectively; the first contact element is arranged to electrically connect the poly gate segment to the first conductive portion, and the second contact element is arranged to electrically isolate the poly gate segment from the second conductive portion (Claim 3).
Regarding claim 6: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the first contact element and the third contact element are in contact with a conductive portion of the conductive layer, the first contact element is arranged to electrically connect the poly gate segment to the conductive portion, and the third contact element is arranged to electrically isolate the first source/drain region from the conductive portion (Claim 3).
Regarding claim 7: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the first contact element and the third contact element are in contact with a conductive portion of the conductive layer, the first contact element is arranged to electrically isolate the poly gate segment from the conductive portion, and the third contact element is arranged to electrically connect the first source/drain region to the conductive portion (Claim 4).
Regarding claim 8: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the third contact element and the fourth contact element are in contact with a conductive portion of the conductive layer; the conductive portion of the conductive layer is coupled to a supply voltage, and the third contact element is electrically isolate the first source/drain region to the conductive portion of the conductive layer (Claim 6).
Regarding claim 9: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the at least one electrically non-conductive contact element comprises a conductive segment and a non-conductive segment stacked one upon the other (Claim 7).
Regarding claim 10 Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
further comprising: a fifth contact element, formed on the first source/drain region, wherein the fifth contact element is formed under and in contact with the conductive layer; one of the third contact element and the fifth contact element is electrically connect the first source/drain region to the conductive layer, and the other of the third contact element and the fifth contact element is electrically isolate the first source/drain region from the conductive layer (Claim 8).
Regarding claim 11: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the first contact element and the second contact element are in contact with a first conductive portion and a second conductive portion of the conductive layer, respectively; the semiconductor device further comprises: a first conductive line, electrically connected to the first conductive portion; a second conductive line, electrically connected to the second conductive portion, and arranged parallel to the first conductive line; a third conductive line formed at a level higher than each of the first conductive line and the second conductive line, the third conductive line crossing over the first conductive line and the second conductive line; a fifth contact element, formed on the first conductive line and in contact with the third conductive line; and a sixth contact element, formed on the second conductive line and in contact with the third conductive line, wherein at least one of the fifth contact element and the sixth contact element is electrically non-conductive (Claim 9).
Regarding claim 12: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the first contact element is in contact with a first conductive portion of the conductive layer; the semiconductor device further comprises: a first conductive line, electrically connected to the first conductive portion of the conductive layer; a plurality of second conductive lines, formed at a level higher than the first conductive line, wherein the second conductive lines are arranged parallel to each other, and cross over the first conductive line; and a plurality of fifth contact elements, formed on different portions of the first conductive line respectively, and in contact with the second conductive line, wherein at least one of the fifth contact elements is electrically non-conductive (Claim 10).
Regarding claim 13: Lu teaches the claim limitation of the multiplexer cell of claim 1, on which this claim depends,
wherein the third contact element is in contact with a conductive portion of the conductive layer; the semiconductor device further comprises: a first conductive line, electrically connected to the conductive portion of the conductive layer; a plurality of second conductive lines, formed at a level higher than the first conductive line, wherein the second conductive lines are arranged parallel to each other, and cross over the first conductive line; and a plurality of fifth contact elements, formed on different portions of the first conductive line respectively, and in contact with the second conductive lines respectively, wherein at least one of the fifth contact elements is electrically non-conductive (Claim 11).
Regarding independent claim 14: Lu teaches (e.g., Claims 13-20) a multiplexer cell, comprising:
a conductive layer, formed over a semiconductor substrate; a plurality of pairs of transistors, formed on the semiconductor substrate, each pair of transistors comprising a p-channel transistor and an n-channel transistor; and an interconnect structure, the p-channel transistor and the n-channel transistor being located at opposite sides of the interconnect structure, the interconnect structure comprising: a first conductive line and a second conductive line arranged in parallel, each of the first conductive line and the second conductive line being located in a first conductive layer and extending along a first direction, wherein each of the first conductive line and the second conductive line is connected between a gate structure of the p-channel transistor and a gate structure of the n-channel transistor; a plurality of third conductive lines arranged in parallel, each third conductive line being located in a second conductive layer at a level different from the first conductive layer, each third conductive line extending along a second direction perpendicular to the first direction; and a plurality of contact elements, formed between the first conductive layer and the second conductive layer, wherein each contact element is formed on one of the first conductive line and the second conductive line, and in contact with one of the third conductive lines, and at least one of the contact elements is electrically non-conductive (Claim 13).
Regarding claim 15: Lu teaches the claim limitation of the multiplexer cell of claim 14, on which this claim depends,
wherein the at least one electrically non-conductive contact element comprises a conductive segment and a non-conductive segment stacked one upon the other (Claim 14).
Regarding claim 16: Lu teaches the claim limitation of the multiplexer cell of claim 14, on which this claim depends,
wherein the first conductive line is electrically connected to a poly gate segment of the gate structure of the p-channel transistor, and the second conductive line is electrically isolated from the poly gate segment of the gate structure of the p-channel transistor (Claim 15).
Regarding claim 17: Lu teaches the claim limitation of the multiplexer cell of claim 16, on which this claim depends,
wherein the first conductive line is further electrically connected to a poly gate segment of the gate structure of the n-channel transistor; the p-channel transistor and the n-channel transistor serve as an inverter of the multiplexer cell (Claim 15).
Regarding claim 18: Lu teaches the claim limitation of the multiplexer cell of claim 14, on which this claim depends,
wherein the first conductive line is electrically isolated from a poly gate segment of the gate structure of the n-channel transistor, and the second conductive line is electrically connected to the poly gate segment of the gate structure of the n-channel transistor; the p-channel transistor and the n-channel transistor serve as a transmission gate of the multiplexer cell (Claim 15).
Regarding independent claim 19: Lu teaches (e.g., Claims 1-12) a method for forming a semiconductor device, comprising:
interconnecting a gate structure of a first transistor structure and a gate structure of a second transistor structure through a first conductive line and a second conductive line, the first conductive line and the second conductive line being included in a first conductive layer and arranged in parallel;
forming an interlayer dielectric on the first conductive layer;
forming first recesses in the interlayer dielectric to expose first portions of the first conductive line; forming second recesses in the interlayer dielectric to expose second portions of the first conductive line;
partially filling at least one of the first recesses with an insulating material; partially filling at least one of the second recesses with the insulating material; and
filling the first recesses and the second recesses with a conductive material to form a plurality of interlayer contacts, wherein more than one of the interlayer contacts comprises the conductive material and the insulating material stacked one upon the other (Claim 17).
Regarding claim 20: teaches the claim limitation of the method of claim 19, on which this claim depends, further comprising:
forming a second conductive layer on the interlayer dielectric; and patterning the second conductive layer into a plurality of third conductive lines in parallel, wherein each of the third conductive lines extends across the first conductive line and the second conductive line, and each interlayer contact is formed under and in contact with a corresponding third conductive line (Claim 20).
Conclusion
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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