DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant election without traverse Species I-1 shown in Figs. 1-8A in the response (filed 08/18/26) to Restriction Requirements is acknowledged.
Applicant stated that all original Cams 1-20 are read on the elected species. However, independent Claim 11, teaching forming a second groove after bonding of two wafers, is not read on Species I-1, it is read on Species I-3 and the step is shown in Figs. 14-15. Claims 12-15 depend on Claim 11. In addition, a limitation of Claim 10: “an opening of the first groove is capped by a bottom surface of the second semiconductor substrate” is read on Species I-2 and I-3 (shown, correspondingly, in Figs. 12 and 16).
Status of Claims
Claims 10-15 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-9 and 16-20 are examined on merits herein.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 5 recites: “during the dicing, the mechanical cutting process is free of contacting sidewalls of the first and second device layers” Claim 20 has a similar limitation. However, the specification of the application does not support the above statement.
New Matter Objection: The current application claims priority to application 16/559,302, but a subject matter of Claims 5 and 20 is not taught by application 16/559,302; accordingly, the current application is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 5 and 20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
In re Claims 5 and 20: Claim 5 recites: “during the dicing, the mechanical cutting process is free of contacting sidewalls of the first and second device layers”. Claim 20 has a similar limitation. However, the specification of the application, as well as specification of various “parent applications”, including application 16/559,302 - do not support the above statement, which, accordingly, represents a new matter with respect to multiple “parent applications”. Appropriate corrections are required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5, 6, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claims 5 and 20: Claim 5 recites: “during the dicing, the mechanical cutting process is free of contacting sidewalls of the first and second device layers”. Claim 20 has a similar limitation. The recitation is unclear not only because it is not supported by the specification, but in common sense: Based on the specification, the blade cuts through the first and second substrates and passes through grooves of device regions of both wafers. During this move, the blade touches at least points of the first and second grove walls that contact first and second substrates; in addition, the current application does not describe any precautions preventing the blade from accidentally touching other parts of groove’s sidewalls.
Appropriate correction is required to clarify the claim language.
For this Office Action, the above-cited limitation of Claim 5 and similar limitation of Claim 20 were omitted from consideration.
In re Claim 6: Claim 5 recites: “sidewalls of the first and second device layers have a slope smaller than sidewalls of the first and second semiconductor substrate”. The recitation is unclear, since “a slope” depends on a chosen direction – where a slope (angle) can be larger with respect to a vertical axis, it will be smaller with respect to a horizontal axis.
Appropriate correction is required to clarify the claim language.
For this Office Action, based on paragraph 0022 of the published application, the cited limitation was interpreted as: “sidewalls of the first and second device layers have a slope smaller than sidewalls of the first and second semiconductor substrate, the slope is defined as a tangent of an angle formed between a top (bottom) surface of the first or second semiconductor substrate and the sidewall ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki et al. (US 2011/0189820).
In re Claim 1, Sasaki teaches a method, comprising:
receiving (Fig. 3, paragraphs 0077-0078 and 0084) a first wafer 12, the first wafer having a first device layer – comprised devices 40 (Fig.4) - on a first semiconductor substrate 41;
receiving a second wafer 11 (Fig. 3, paragraphs 0077-0078 and 0090), the second wafer having a second device layer – comprised devices 40 (Fig. 4) on a second semiconductor substrate 41;
forming (Fig 7, paragraphs 0091-0092, 0103) a first groove 104 along a first scribing channel of the first wafer 11 with a non-mechanical cutting process (e.g., being a reactive ion etching, paragraph 0092);
forming (Fig. 7, paragraphs 0091-0092, 0103) a second groove 104 along a second scribing channel of the second wafer 12 with a non-mechanical cutting process (e.g., being a reactive ion etching, paragraph 0092);
after the forming of the first and second grooves 103, bonding the first and second wafers together (Figs. 3 and 10, paragraph 0104), wherein the first and second grooves 104 are vertically aligned in the bonded first 12 and second wafers 11; and
dicing (Fig. 25, paragraphs 0131-0132) the bonded first 12 and second 11 wafers through the first and second grooves 104 with a mechanical cutting process.
In re Claim 3, Sasaki teaches the method of Claim 1, wherein the non-mechanical cutting process is a plasma cutting process: Sasaki teaches a reactive plasma etching the grooves, and as is known in the art, the reactive ion etching is created either by a capacitively coupled plasma (CCP-REI) or by an inductively coupled plasma (ICP-RIE).
In re Claim 4, Sasaki teaches the method of Claim 1, wherein the mechanical cutting process (Fig. 25, paragraph 0131) uses a saw or a blade – Sasaki teaches a dicing saw.
In re Claim 5, Sasaki teaches the method of Claim 1, wherein, during the dicing, the mechanical cutting process is free of contacting sidewalls of the first and second device layers (e.g., as interpreted, even though Sasaki shows that a saw creates an opening significantly narrower than a groove).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Lei et al. (US 2013/0267076).
In re Claim 2, Sasaki teaches the method of Claim 1 as cited above and wherein the non-mechanical cutting process is RIE, being a plasma cutting process. Sasaki does not teach that the non-mechanical cutting process is a laser cutting process.
Lei teaches (paragraph 0008) that plasma dicing is cost-effective and may also be prohibited in case where plasma ions are met with metals. Lei suggests substituting plasma dicing with laser dicing and creating at least an initial groove 210 (Figs. 2A-2B, paragraphs 0034-0036) through a device layer 206 exposing a top of a substrate 204 on which the device layer 206 is disposed.
Sasaki and Lei teach analogous arts directed to a multi-step singulation of chips from a wafer, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sasaki method in view of the Lei teaching, since they are from the same field of endeavor, and the Lei method created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki method of Claim 1 by substituting the plasma dicing with a laser dicing, when it is desirable at least to save on the manufacturing cost.
In re Claim 7, Sasaki teaches the method of Claim 1 as cited above, but does not teach that after the dicing, sidewalls of the first and second device layers – created by the RIE - have a surface roughness larger than sidewalls of the first and second semiconductor substrates – created by a dicing blade.
Lei teaches (paragraph 0008) that plasma dicing is cost-effective and may also be prohibited in case where plasma ions are met with metals. Lei suggests substituting plasma dicing with laser dicing and creating at least an initial groove 210 (Figs. 2A-2B, paragraphs 0034-0036) through a device layer 206 exposing a top of a substrate 204 on which the device layer 206 is disposed.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki method of Claim 1 by substituting the plasma dicing with a laser dicing, when it is desirable at least to save on the manufacturing cost.
With this modification, it would be inherent for the structure created by the Sasaki/Lei method that sidewalls of the first and second device layers created by laser have a surface roughness larger than sidewalls of the first and second semiconductor substrates created by the dicing blade: Yoshida (US 2015/0371966) teaches (Fig. 5, paragraphs 0031-0032) that a blade dicing creates a surface roughness significantly lower than laser dicing creates.
In re Claim 8, Sasaki teaches the method of Claim 1 as cited above, including forming the first and second grooves, but does not teach, at least, explicitly, that after the forming of the first and second grooves, the first groove extends fully through the first device layer, and the second groove extends fully through the second device layer.
Lei teaches (Figs. 2A-2C) that at a groove 210 is formed through a device layer 206 (paragraph 0036) up to a depth of disposing substrate 204 on which the device layer 206 is formed.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki device and method by forming the first and second grooves to be fully extending through the first and second device layers till exposing a surface of the first and second substrates (on which the device layer are formed, accordingly), in order to enable repeatability of the device structure in the manufacturing process.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Hsu et al. (US 2010/0171171).
In re Claim 6, Sasaki teaches the method of Claim 1 as cited above, wherein, the first and second grooves, passing at least through a device layer (Sasaki, paragraph) are created by the RIE.
Sasaki does not teach that after the dicing, sidewalls of the first and
second device layers have a slope smaller than sidewalls of the first and second semiconductor substrates – sidewalls of his grooves 104 and sidewalls of the substrates are parallel to each other and perpendicular to exposed bottom surfaces of both substrates.
Hsu teaches (Figs. 1-2, paragraph 0018) that RIE may create sidewalls shown by Sasaki (such as having a slope angle 90o) or, depending on parameters of RIE, sidewalls may be created having a smaller slope (as Fig. 1B shows).
Sasaki and Hsu teach analogous arts directed to a RIE, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying/understanding the Sasaki method (and device) in view of the Hsu teaching, since they are from the same field of endeavor, and Hsu created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki device and method by choosing parameters of the RIE such that the sidewalls of grooves have a slope smaller than sidewalls of the first and second substrates, when such shapes of grooves are preferred for the manufacturer. Note that in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Sekiya (US 2019/0081021).
In re Claim 9, Sasaki teaches the method of Claim 1 as cited above, wherein after the bonding of the first and second wafers (Fig. 10), openings of the first and second grooves face each other.
Sasaki does not teach that the openings of the first and second grooves directly face each other, since in the Sekiya structure, electrodes 32 (Fig. paragraph) are disposed on each of grooves 103.
Sekiya teaches (Fig. 13, paragraph 0059) that after creation of a stacked wafer assembly, openings 28 (paragraph 0042) created in two wafers directly face each other.
Sasaki and Sekiya teach analogous arts directed to a method comprised a singulation of two stacked dies from a structure comprised a repeating structure of stacked dies, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sasaki device and method in view of the Sekiya device and method, since they are from the same field of endeavor, and Sekiya method created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki device by removing electrodes formed over the grooves, creating by that first and second grooves directly facing each other, wherein it is desirable having no electrodes at edges of two stacked semiconductor dies.
Claims 16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Yamazaki (JP 2864624) and Wang et al. (US 2013/0307165).
In re Claim 16, Sasaki teaches a method, comprising:
forming (obviously, see Fig. 3 for wafer 12) a first dielectric layer 31a (paragraphs 0078-0084) over a first silicon-containing substrate 41 (Fig. 4), the first dielectric layer 31a containing a first electrode 32Aa (Fig. 3, paragraphs 0079 teaches that the insulating layer 31 surrounds electrode 32Aa);
forming (obviously, see Fig. 3 for wafer 11) a second dielectric layer 31b (paragraphs 0078-0084) over a second silicon-containing substrate 41 (Fig. 4), the second dielectric layer 31b containing a second electrode 32Aa; and
bonding the first dielectric layer to the second dielectric layer through insulating adhesive 111 (Fig. 10, paragraph 0104).
Sasaki does not teach that each of the first and second electrodes is created as a stack of a metal silicide feature and a bonding medium, the bonding medium including tungsten, and wherein bonding the first dielectric layer to the second dielectric layer is made through the first bonding medium and the second bonding medium (both mediums being tungsten). However, Sasaki teaches bonding electrodes 32, not disclosing their material.
Yamazaki teaches a contact comprised a stack of the tungsten silicide and tungsten (Claim 1).
Sasaki and Yamazaki teach analogous arts directed to conductive contacts/electrodes/pads, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sasaki device and method in view of the Yamazaki teaching, since they are from the same field of endeavor, and Yamazaki created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki device and method by creating their electrodes/pads 32 as stacks of tungsten silicide and tungsten, per Yamazaki, in order to materially enable creation of these elements.
Sasaki/Yamazaki does not teach that bonding the first dielectric layer to the second dielectric layer is made through the first bonding medium and the second bonding medium. However, Sasaki teaches that during bonding (Fig. 10) pads/electrodes 32 of opposite wafers are disposed opposite to each other.
Wang teaches (Figs. 2A-2C, paragraph 0076) bonding dielectrics of two opposed wafers through bonding of pads/electrodes 21 and 23 of these wafers.
Sasaki/Yamazaki and Wang teaches analogous arts directed to creation of a stack of two wafers bonding to each other, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sasaki/Yamazaki device and method in view of the Wang teaching, since they are from the same field of endeavor, Wang created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki/Yamazaki method by removing the insulating adhesive layer 111 between two bonded wafers and to bond the first and second dielectric layers through the first and second bonding mediums, (which are created as tungsten of Yamazaki), wherein it is desirable to avoid disposing an insulating adhesive between two bonded wafers.
In re Claim 18, Sasaki/Yamazaki/Wang teaches the method of Claim 16 as cited above.
Sasaki further teaches (Figs. 3- 10) prior to the bonding (Fig. 10), forming (Figs. 6-7, paragraph 0091) a first groove 104 through the first dielectric layer 31 (which is a top layer of a first wafer 12, as Fig. 3 shows), and a second groove 104 through the second dielectric layer 31 (created similar to the structure of the first wafer); and
after the bonding, dicing (Fig. 25, paragraphs 0131-0132) through the first and second grooves 104 and the first and second silicon-containing substrates 41.
In re Claim 20, Sasaki/Yamazaki/Wang teaches the method of Claim 18 as cited above, wherein the dicing is free of contacting sidewalls of the first and second grooves (e.g., in accordance with the claim interpretation).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki/Yamazaki/Wang in view of Chitnis et al. (US 2008/0179611).
In re Claim 17, Sasaki/Yamazaki/Chitnis teaches the method of Claim 16 as cited above, wherein, as shown for Claim 16, the first and second metal silicide features each include tungsten silicide, but does not teach that the first and second silicon-containing substrate each include silicon carbide.
Chitnis teaches (paragraph 0063) such silicon-containing substrate as silicon carbide.
Sasaki/Yamazaki/Wang and Chitnis teach analogous arts directed to a wafer comprised a substrate and a device layer, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sasaki/Yamazaki/Wang device and method in view of Chitnis teaching, since they are from the same field of endeavor, and Chitnis created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki/Yamazaki/Wang device and method by substituting the first and second silicon substrate of Sasaki with SiC substrate, wherein it is desirable having substrates with a very high thermal conductivity (Chitnis, paragraph 0063).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki/Yamazaki/Wang in view of Lei.
In re Claim 19, Sasaki/Yamazaki/Wang teaches the method of Claim 18 as cited above.
Sasaki further teaches the forming of the first and second grooves 104 (Figs. 6-7) with a plasma dicing, such as with RIE (paragraphs 0091-0092) and the dicing (of Fig. 25) made by a mechanical cutting process (paragraphs 0131-0132).
Sasaki does not teach creating the grooves by a laser.
Lei teaches (paragraph 0008) that plasma dicing is cost-effective and may also be prohibited in case where plasma ions are met with metals. Lei suggests substituting plasma dicing with laser dicing and creating at least an initial groove 210 (Figs. 2A-2B, paragraphs 0034-0036) through a device layer 206 exposing a top of a substrate 204 on which the device layer 206 is disposed.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sasaki/Yamazaki/Wang method of Claim 18 by substituting the plasma dicing with a laser dicing, when it is desirable at least to save on the manufacturing cost.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 08/28/26
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