DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 07/30/2024 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 17, it is unclear as to what the “second work function metal layer” is pertaining to. There appears to only be one work function metal layer shown in the drawings and that the “first work function metal layer” is the same layer as the “second work function metal layer”. Please provide clarity.
Claims 18-20 are rejected due to their dependency on claim 17.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 8-9, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2021/0083054 A1), hereafter “Liaw”, and further in view of Lee et al. (US 2020/0381432 A1), hereafter “Lee”.
As to claim 1, Liaw teaches a semiconductor structure, comprising:
a substrate (202, Fig. 2, ⁋ [0014]);
first channel layers vertically stacked over the substrate in a first region having a first conductivity type (214-1 right, ⁋ [0033], Fig. 6);
second channel layers (214-1 left) vertically stacked over the substrate in a second region and adjacent to the first channel layers, the second region having a second conductivity type that is opposite to the first conductivity type;
a gate dielectric layer (216-1, Fig. 7, ⁋ [0027]) wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer; and
a work function metal layer (208, Fig. 9A) disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.
Liaw fails to teach a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region, wherein the first region is free of the Vt modulation layer.
Lee teaches a similar transistor device where a threshold voltage modulation layer (114a) wraps around semiconductor layers (106b) and not in the first region.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the threshold voltage modulation layer as taught by Lee into the transistor device as taught by Liaw for the desire of threshold voltage adjustment (⁋ [0069]). One skilled in the art would understand the added benefit of controlling the threshold voltage used to turn the transistor on yielding a more reliable device.
As to claim 2, Liaw in view of Lee teaches the semiconductor structure of claim 1, wherein the work function metal layer includes a same composition in the first and second regions (208 shown in both regions).
As to claim 3, Liaw in view of Lee teaches the semiconductor structure of claim 2, wherein the work function metal layer extends continuously from the first region to the second region (208 extends continuously).
As to claim 8, Liaw in view of Lee teach the semiconductor structure of claim 1, but fails to explicitly teach wherein the first channel layers are portions of a pull-up transistor of a memory cell, and the second channel layers are portions of a pull-down transistor of the memory cell.
Examiner notes Liaw does teach the first channel layers as part of a p-type transistor and second channel layers as part of a n-type transistor and Lee teaches a p-type transistor (⁋ [0030]) as a pull-up transistor (⁋ [0187]) and a n-type transistor (⁋ [0029]) as a pull-down transistor (⁋ [0186])
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching of Lee’s pull-up and pull-down transistors into the device of Liaw modified by Lee for the purpose of creating an SRAM cell which may be provided as the embedded memory and/or cache memory (⁋ [0176]). When the SRAM is embedded in the semiconductor chip, the consumption of the active power of the electronic device may be reduced (⁋ [0171]).
As to claim 9, Liaw in view of Lee teaches the semiconductor structure of claim 1, but fails to explicitly teach wherein a thickness of the first channel layers is larger than a thickness of the second channel layers.
Liaw does teach, however, in terms of threshold voltage, channel member width is substantially inversely proportional to the threshold voltage. That is, a 20% increase in channel width may translate into about 20% decrease in threshold voltage (⁋ [0018]).
Additionally, Lee teaches that it’s channel width W3a of the nanosheets 106a not covered with a voltage modulation layer are greater than the channel width W3b of the nanosheets 106b covered with the voltage modulation layer 116b (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the channel widths of Liaw in view of Lee, making the channel layers covered by the voltage modulation layer smaller, for the purpose of better controlling the threshold voltage.
As to claim 17, Liaw teaches A memory cell, comprising:
first channel layers (214-1 right side 205A, Fig. 9B, ⁋ [0025]) vertically stacked;
a first gate dielectric layer (216-1 right side 205A, ⁋ [0027]) wrapping around each of the first channel layers; and
a first work function metal layer (211-2, ⁋ [0020]) disposed on the first gate dielectric layer and wrapping around each of the first channel layers; and
second channel layers (214-1 left side 205A, Fig. 9B, ⁋ [0025]) vertically stacked;
a second gate dielectric layer (216-1 left side 205A, ⁋ [0027]) disposed on the Vt modulation layer and wrapping around each of the second channel layers; and
a second work function metal layer (211-1, ⁋ [0020]) disposed on the second gate dielectric layer and wrapping around each of the second channel layers,
Liaw fails to teach the first transistor as a part of a pull-up transistor nor the second transistor as part of a pull-down transistor, a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers, and wherein the first and second work function metal layers have a same composition. Examiner notes Liaw does teach the first transistor as an p-type and the second transistor as a n-type.
Lee teaches a similar transistor device where a threshold voltage modulation layer (114a) wraps around semiconductor layers (106b), along with two work function metal layers (118a+118b) having a same composition (⁋ [0072]) and a p-type transistor (⁋ [0030]) as a pull-up transistor (⁋ [0187]) and a n-type transistor (⁋ [0029]) as a pull-down transistor (⁋ [0186]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the threshold voltage modulation layer as taught by Lee into the transistor device as taught by Liaw for the desire of threshold voltage adjustment (⁋ [0069]). One skilled in the art would understand the added benefit of controlling the threshold voltage used to turn the transistor on yielding a more reliable device.
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the same gate composition as taught by Lee into the device of Lee for the purpose of reducing costs and simplifying the production process.
Lastly, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching of Lee’s pull-up and pull-down transistors into the device of Liaw modified by Lee for the purpose of creating an SRAM cell which may be provided as the embedded memory and/or cache memory (⁋ [0176]). When the SRAM is embedded in the semiconductor chip, the consumption of the active power of the electronic device may be reduced (⁋ [0171]).
As to claim 18, Lee in view of Liaw teach the memory cell of claim 17, Lee further teaches wherein the first and second work function metal layers are portions of a same continuous work function metal layer (⁋ [0070], “The first gate electrode 118a and the second gate electrode 118b may be connected to each other.”)
As to claim 19, Lee in view of Liaw teaches the memory cell of claim 17, but fails to explicitly teach wherein a thickness of the first channel layers is larger than a thickness of the second channel layers.
Liaw does teach, however, in terms of threshold voltage, channel member width is substantially inversely proportional to the threshold voltage. That is, a 20% increase in channel width may translate into about 20% decrease in threshold voltage (⁋ [0018]).
Additionally, Lee teaches that it’s channel width W3a of the nanosheets 106a not covered with a voltage modulation layer are greater than the channel width W3b of the nanosheets 106b covered with the voltage modulation layer 116b (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the channel widths of Liaw in view of Lee, making the channel layers covered by the voltage modulation layer smaller, for the purpose of better controlling the threshold voltage.
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2021/0083054 A1), hereafter “Liaw”, and further in view of Ando et al. (US 2019/0280107 A1), hereafter “Ando”.
As to claim 4, Liaw in view of Lee teach the semiconductor structure of claim 1, but fails to teach wherein the Vt modulation layer includes germanium.
Ando teaches a similar device wherein a work function adjusting material (15, Fig. 3, ⁋ [0053]) is placed around a channel layer made of germanium (⁋ [0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the germanium work function adjustment layer as taught by Ando for the voltage adjustment layer of Liaw and Lee as it is taught to also be a viable layer with the same function.
As to claim 7, Liaw in view of Lee and Ando teach the semiconductor structure of claim 4, Ando further teaches wherein a concentration of germanium in the Vt modulation layer ranges from about 40% to about 100% (⁋ [0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the range as taught by Ando because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Allowable Subject Matter
Claims 11-16 are indicated allowed.
As to claim 11, Liaw and Lee are the closest prior art and fail to disclose the first and second portions of the Vt modulation layer include a same dopant but with different concentrations.
Claims 5-6, 10, and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 5, Liaw in view of Lee are the closest prior art and fail to teach wherein a concentration of germanium in the Vt modulation layer is non-uniform.
As to claim 6, Liaw in view of Lee are the closest prior art and fail to teach wherein a concentration of germanium in the Vt modulation layer is substantially uniform.
As to claim 10, Liaw in view of Lee are the closest prior art and fail to teach wherein the thickness of the first channel layers substantially equals a sum of the thickness of the second channel layers and two times of a thickness of the Vt modulation layer.
As to claim 20, Liaw in view of Lee are the closest prior art and fail to teach wherein a thickness of the Vt modulation layer is about 10% to about 30% of a thickness of the second channel layers.
Conclusion
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/CARNELL HUNTER III/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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