DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending in this application.
Information Disclosure Statement
Acknowledgment is made that the information disclosure statement has been received and considered by the examiner. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Drawings
There are no objections or rejections to the drawings.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 8-14 and 16-19 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (US Patent Application Publication No 2019/0148623) hereinafter referred to as Liao.
Per Claim 1 Liao discloses a semiconductor device, ( see figures 8-13) comprising
a bottom electrode (140’);
a magnetic tunneling junction (MTJ) element (150’) over the bottom electrode, the MTJ element including a top magnetic plate (153’), a bottom magnetic plate (151), and a barrier layer (152) between the top magnetic plate and the bottom magnetic plate (as shown in figure 8), an edge portion of the bottom magnetic plate (151) extending beyond sidewalls of the top magnetic plate (153’) (as shown in figure 8);
a spacer (180/190) disposed on the sidewalls of the top magnetic plate but not on sidewalls of the bottom magnetic plate (as shown in figure 8); (The examiner notes that the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween) and
a top electrode (160”) over the top magnetic plate
Per Claim 2 Liao discloses the device of claim 1 including where the spacer (180/190) covers a top surface of the edge portion of the bottom magnetic plate (151). (as shown in fig. 8)
Per Claim 5 Liao discloses the device of claim 1 including where a dielectric layer (120/210/220) covering an outer sidewall of the spacer (180/190) and the sidewalls of the bottom magnetic plate (151’) (see figures 10-11).
Per Claim 8 Liao discloses the device of claim 5 including where a bottom potion of the dielectric layer (120/210/220) is below a bottom surface of the bottom electrode (140’).
Per Claim 9 Liao discloses the device of claim 1 including where an edge portion of the barrier layer (152) extends beyond the sidewalls of the top magnetic plate (153), and the spacer (180/190) is not disposed on sidewalls of the barrier layer (152).
Per Claim 10 Liao discloses the device of claim 9 including where the spacer (180/190) covers a top surface of the edge portion of the barrier layer (152’) (see figure 12).
Per Claim 11 Liao discloses a semiconductor device, ( see figures 8-13) comprising
a bottom electrode (140’);
a magnetic tunneling junction (MTJ) element (150’) over the bottom electrode, the MTJ element including a top magnetic plate (153’), a bottom magnetic plate (151), and a barrier layer (152) between the top magnetic plate and the bottom magnetic plate (as shown in figure 8), the bottom magnetic plate (151) including a pinning layer (see [0020] an anti-ferromagnetic material (AFM) layer) and a pinned layer (ferromagnetic pinned layer) disposed on the pinning layer,
an edge portion of the pinning layer (part of 151) extending beyond sidewalls of the top magnetic plate (153’) (as shown in figure 8);
a spacer (180/190/210) disposed on the sidewalls of the top magnetic plate but not on sidewalls of the pinning layer (as shown in figures 8-13); and
a top electrode (160”) over the top magnetic plate
Per Claim 12 Liao discloses the device of claim 11 including where the spacer (180/190/210) covers a top surface of the edge portion of the pinning layer and sidewalls of the pinned layer (151). (as shown in fig. 12)
Per Claim 13 Liao discloses the device of claim 11 including where an edge portion of the barrier layer (152) extends beyond the sidewalls of the top magnetic plate (153), and the spacer (180/190/210) is not disposed on sidewalls of the barrier layer (152).
Per Claim 14 Liao discloses the device of claim 11 including where an edge portion of the pinned layer (part of 151) extends beyond the sidewalls of the top magnetic plate (153’), and the spacer (180/190/210) is not disposed on sidewalls of the edge portion of the pinned layer. (as shown in figures 8-13).
Per Claim 16 Liao discloses the device of claim 11 including a dielectric (220) layer covering an outer sidewall of the spacer and the sidewalls of the pinning layer. (see figures 8-13)
Per Claim 17 Liao discloses a semiconductor device, ( see figures 8-13) comprising
a bottom electrode (140’);
a magnetic tunneling junction (MTJ) element (150’) over the bottom electrode, the MTJ element including a top magnetic plate (153’), a bottom magnetic plate (151), and a barrier layer (152) between the top magnetic plate and the bottom magnetic plate (as shown in figure 8), an edge portion of the barrier layer (152) and an edge portion of the bottom magnetic plate (151) extending beyond sidewalls of the top magnetic plate (153’) (as shown in fig. 8);
a spacer (180/190/210) disposed on the sidewalls of the top magnetic plate (153’) (as shown in figures 8-13) and on a top surface of the edge portion of the barrier layer (152); and
a top electrode (170’) over the top magnetic plate.
Per Claim 18 Liao discloses the device of claim 17 including where the spacer is not disposed on sidewalls of the barrier layer and sidewalls of the bottom magnetic plate. (as shown in figure 8)
Per Claim 19 Liao discloses the device of claim 17 including a dielectric layer (220) covering an outer sidewall of the spacer, sidewalls of the barrier layer, and sidewalls of the bottom magnetic plate. (see figure 13)
Allowable Subject Matter
Claims 3-4, 6-7, 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Peng (US 2020/0136026) is cited for teaching an analogous device that includes m ost of the features of claim 1 but not a spacer (180/190) disposed on the sidewalls of the top magnetic plate but not on sidewalls of the bottom magnetic plate.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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