CTNF 18/788,483 CTNF 82317 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12,147,784 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the later clearly dominate the claims of the instant application. For example, claim 1 of the instant application is substantially similar to claim 10 of the ‘784 patent with the difference of the instant application claiming an “adder tree circuit” vs ‘784 “adder circuit”. While ‘784 is narrower in scope as claiming a particular type of adder circuit, it is a mere obvious species of adder circuits that are notoriously common and well-known in the art . Allowable Subject Matter Claims 1-20 are thought to be in an acceptable condition for allowance pending Applicant’s overcoming the outstanding ODP rejections above. Regarding claim 1 , while the prior art teaches various embodiments of CIM including adder tree and signed weight signals (see Feng and Li), the prior art fails to teach or reasonably suggest in combination all of the features of the claim including an adder tree circuit configured to receive the plurality of product signals from the plurality of logic circuits, wherein the adder tree circuit is configured to receive a weight sign signal indicating whether the weight signal is signed and out a partial sum signal based on the product signals and the weight sign signal. Regarding claim 10 , while the prior art teaches various embodiments of CIM including adder tree and signed weight signals (see Feng and Li), the prior art fails to teach or reasonably suggest in combination all of the features of the claim including ; a register configured to store a weight sign bit; and an adder circuit connected to outputs of the first and second multiply circuits and the register, and configured to add weight sign signals associated with the first and second weight signals. Regarding claim 17 , while the prior art teaches various embodiments of CIM including adder tree and signed weight signals (see Feng and Li), the prior art fails to teach or reasonably suggest in combination all of the features of the claim including a register configured to store a weight sign bit; and an adder circuit connected to output terminals of the plurality of multiply circuits and the register, wherein the adder circuit is configured to add the product signals and output a partial sum signal based on the weight sign bit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS KING/Primary Examiner, Art Unit 2824 Application/Control Number: 18/788,483 Page 2 Art Unit: 2824 Application/Control Number: 18/788,483 Page 3 Art Unit: 2824 Application/Control Number: 18/788,483 Page 4 Art Unit: 2824
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