DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of provisional application 63/225,016 submitted on 7/23/2021 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 7/30/2024 and IDS filed on 12/5/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-7, 9, 11, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2007/0108433; hereinafter ‘Lee’).
Regarding claim 1, Lee teaches a phase change random access memory (PCRAM) (a semiconductor memory device employing a phase change process using chalcogenide material layer 40, FIG. 2, [0033, 0044]; hereinafter ‘PCRAM’) comprising:
a wafer (semiconductor substrate 10 corresponding to the claimed wafer, [0034, 0048]);
a field effect transistor (FET) logic layer (a transistor device layer comprising 20, 21, and 22, [0034]; hereinafter ‘LL’) disposed on the wafer (10) and including at least one heating FET (transistor 20 controlling current supplied to 40, [0043-0044]) for each storage cell (the memory cell storing data using 40, [0043-0044]; hereinafter ‘SC’) of the PCRAM (PCRAM); and
a storage layer (a data storing layer comprising 40, 42, and 50, [0035, 0038]; hereinafter ‘SL’) disposed on the FET logic layer (LL) and including a region of a phase change material (patterned regions of 40 comprising a Te-Ge-Sb phase change material, [0035, 0043-0044]; hereinafter ‘40R’) for each storage cell (SC) that is electrically connected to a channel of the at least one heating FET of the storage cell (40 of SC being electrically connected to the channel between source region 11 and drain region 12 of 20 of SC through 36, 24, and 11, [0036-0037, 0043]).
Regarding claim 5, Lee teaches the PCRAM of claim 1 wherein the phase change material comprises a chalcogenide material (40 comprising a chalcogenide material such as Te-Ge-Sb, [0035]).
Regarding claim 6, Lee teaches the PCRAM of claim 5 wherein the phase change material comprises a germanium antimony telluride (GST) or titanium antimony telluride (TST) composition (40 comprising a germanium antimony telluride such as Te-Ge-Sb, [0035]).
Regarding claim 7, Lee teaches the PCRAM of claim 1 further comprising:
a dielectric layer (32 made of SiO2, FIG. 2, [0037, 0039]) interposed between the FET logic layer and the storage layer (32 interposed LL and SL); and
electrically conductive plugs (36 made of TiAlN, FIG. 2, [0037]) passing through the dielectric layer interposed between the FET logic layer and the storage layer (36 formed in and filling 32a passing through 32, [0052-0053]);
wherein the regions of the phase change material (40R, FIG. 2) are disposed on the electrically conductive plugs (40 being formed on 36, [0054]) and are electrically connected to the channels of the corresponding at least one heating FETs of the storage cell by the electrically conductive plugs (40 being electrically connected to the channel between 11 and 12 of 20 of SC through 36, FIG. 2).
Regarding claim 9, Lee teaches a phase change random access memory (PCRAM) (a semiconductor memory device employing a phase change process using chalcogenide material layer 40, FIG. 2, [0033, 0044]; hereinafter ‘PCRAM’) comprising:
a wafer (semiconductor substrate 10 corresponding to the claimed wafer, [0034, 0048]);
a storage layer (a data storing layer comprising 40, 42, and 50, [0035, 0038]; hereinafter ‘SL’) including a region of a chalcogenide material (patterned regions of 40 comprising a Te-Ge-Sb phase change material, [0035, 0043-0044]; hereinafter ‘40R’) for each storage cell (the memory cell storing data using 40, [0043-0044]; hereinafter ‘SC’) of the PCRAM (PCRAM); and
a field effect transistor (FET) logic layer (a transistor device layer comprising 20, 21, and 22, [0034]; hereinafter ‘LL’) interposed between the wafer (10) and the storage layer (SL) and including at least one heating FET (transistor 20 controlling current supplied to 40, [0043-0044]) for each storage cell (SC) that is electrically connected to heat the chalcogenide material of the storage cell (20 being electrically connected to 40 through 11, 24, and 36, whereby the controlled current heats 40, [0036-0037, 0043-0044]).
Regarding claim 11, Lee teaches the PCRAM of claim 9 wherein the chalcogenide material comprises a germanium antimony telluride (GST) composition (40 comprising a germanium antimony telluride such as Te-Ge-Sb, [0035]).
Regarding claim 16, Lee teaches a phase change random access memory (PCRAM) (a semiconductor memory device employing a phase change process using chalcogenide material layer 40, FIG. 2, [0033, 0044]; hereinafter ‘PCRAM’) comprising:
a wafer (semiconductor substrate 10 corresponding to the claimed wafer, [0034, 0048]);
heating field effect transistors (FETs) (20 controlling channel current supplied through conductive plug 24 and heating material layers 36 to heat respective chalcogenide material layers 40, [0034, 0036-0037, 0043-0044]) disposed on the wafer (10);
a dielectric layer (the interlayer dielectric structure comprising 32 and 42, wherein 32 is made of SiO2, FIG. 2, [0037-0039]; hereinafter ‘DL’) disposed on the heating FETs (20); and
regions of phase change material (patterned regions of 40 comprising a Te-Ge-Sb phase change material, [0035, 0043-0044]; hereinafter ‘40R’) embedded in the dielectric layer (40R being formed on second on 32 and subsequently covered and laterally surrounded by 42, FIG. 2, [0038, 0054]) disposed on the heating FETs (20) and electrically connected to the heating FETs to form PCRAM storage cells (40R being electrically connected to respective transistors 20 through 36 and 24, and source region 11, whereby transistor controlled current heats 40R to change its phase and store data, [0036-0037, 0043-0044]).
Regarding claim 17, Lee teaches the PCRAM of claim 16 further comprising:
electrically conductive plugs (36 comprising TiAlN, FIG. 2, [0037]) embedded in the dielectric layer disposed on the heating FETs (36 formed within via holes 32a in 32 above respective transistor 20, [0037, 0052-0053]);
wherein the regions of phase change material (40R) are disposed on the electrically conductive plugs (40R formed on 36) and are electrically connected to the heating FETs via the electrically conductive plugs to form the PCRAM storage cells (40R electrically connected through 36 and 24 to 11 of respective 20, whereby transistor controlled current flows through 36 to heat 40 and perform phase change data storage, FIG. 2, [0036-0037, 0043-0044, 0054]).
Regarding claim 18, Lee teaches the PCRAM of claim 16 wherein the phase change material comprises a chalcogenide material (40 comprising a chalcogenide material such as Te-Ge-Sb, [0035]).
Regarding claim 19, Lee teaches the PCRAM of claim 16 wherein the phase change material comprises a germanium antimony telluride (GST) or titanium antimony telluride (TST) composition (40 comprising a germanium antimony telluride such as Te-Ge-Sb, [0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2007/0108433) in view of Juengling (US 2014/0185355).
Regarding claim 2, Lee teaches the PCRAM of claim 1, but does not teach the PCRAM wherein the storage layer further includes: a second heating transistor for each storage cell that includes a channel electrically connected to the phase change material of the storage cell.
Juengling teaches a PCRAM (an array of cells 186 having phase-change memory element connected to source 192 or drain 194, FIGS. 24 and 27, [0005, 0043-0045, 0061]) wherein the storage layer (a vertically extending storage device region including lower transistor 190, upper transistor 188, and the phase-change memory element, FIGS. 25-26, [0044, 0061]) further includes:
a second heating transistor (188 formed by gates 180 and 182, FIG. 25, [0047]) for each storage cell (each dual-transistor cell 186, [0043-0044]) that includes a channel (upper channel 214 established by row gates 180 and 182, FIG. 29, [0050]) electrically connected to the phase change material of the storage cell (214 electrically connected through 192 or 194 to phase-change memory element, [0050, 0061]).
As taught by Juengling, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM wherein the storage layer further includes: a second heating transistor for each storage cell that includes a channel electrically connected to the phase change material of the storage cell as claimed, because vertically stacking the transistors provides the functionality of a multi-transistor cell while reducing the lateral cell area compared with arranging the transistors side-by-side [0015-0017].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Juengling in combination with Lee due to the above reason.
Regarding claim 10, Lee teaches the PCRAM of claim 9, wherein a heating transistor for each storage cell that is electrically connected to heat the chalcogenide material of the storage cell (20 being electrically connected to 40 through 11, 24, and 36, whereby the controlled current heats 40, [0036-0037, 0043-0044]).
Lee does not teach the PCRAM wherein the storage layer further includes a second transistor for each storage cell.
Juengling teaches a PCRAM (an array of cells 186 having phase-change memory element connected to source 192 or drain 194, FIGS. 24 and 27, [0005, 0043-0045, 0061]) wherein the storage layer (a vertically extending storage device region including lower transistor 190, upper transistor 188, and the phase-change memory element, FIGS. 25-26, [0044, 0061]) further includes a second transistor (188 formed by gates 180 and 182, FIG. 25, [0047]) for each storage cell (each dual-transistor cell 186, [0043-0044]).
As taught by Juengling, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM wherein the storage layer further includes a second transistor for each storage cell as claimed, because vertically stacking the transistors provides the functionality of a multi-transistor cell while reducing the lateral cell area compared with arranging the transistors side-by-side [0015-0017].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Juengling in combination with Lee due to the above reason.
Regarding claim 14, Lee teaches the PCRAM of claim 9, but does not teach the PCRAM wherein the storage layer further includes: a second heating transistor for each storage cell that includes a channel electrically connected to the phase change material of the storage cell.
Juengling teaches a PCRAM (an array of cells 186 having phase-change memory element connected to source 192 or drain 194, FIGS. 24 and 27, [0005, 0043-0045, 0061]) wherein the storage layer (a vertically extending storage device region including lower transistor 190, upper transistor 188, and the phase-change memory element, FIGS. 25-26, [0044, 0061]) further includes:
a second heating transistor (188 formed by gates 180 and 182, FIG. 25, [0047]) for each storage cell (each dual-transistor cell 186, [0043-0044]) that includes a channel (upper channel 214 established by row gates 180 and 182, FIG. 29, [0050]) electrically connected to the phase change material of the storage cell (214 electrically connected through 192 or 194 to phase-change memory element, [0050, 0061]).
As taught by Juengling, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM wherein the storage layer further includes: a second heating transistor for each storage cell that includes a channel electrically connected to the phase change material of the storage cell as claimed, because vertically stacking the transistors provides the functionality of a multi-transistor cell while reducing the lateral cell area compared with arranging the transistors side-by-side [0015-0017].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Juengling in combination with Lee due to the above reason.
Claims 3, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2007/0108433) in view of Juengling (US 2014/0185355), and further in view of RIOS et al. (US 2019/0252020; hereinafter ‘RIOS’).
Regarding claim 3, Lee in view of Juengling teaches the PCRAM of claim 2, but does not teach wherein the second heating transistor includes a channel comprising an indium gallium zinc oxide composition.
RIOS teaches a vertically integrated resistive memory device (the 2T-1R memory cell integrated in backend layers between metal layers M1-M3, FIG. 8, [0015-0017, 0039-0040]) wherein the second heating transistor (the write transistor corresponding to the claimed the second heating transistor (the driving transistor) formed over common node N212, [0042]) includes a channel (IGZO channel layer 210 formed between common node/drain 212 and source 214, [0043]) comprising an indium gallium zinc oxide composition (210 is IGZO layer, [0043]).
As taught by RIOS, one of ordinary skill in the art would utilize and modify the above teaching into Lee in view of Juengling to obtain and achieve the PCRAM wherein the second heating transistor includes a channel comprising an indium gallium zinc oxide composition as claimed, because IGZO channel is suitable for forming a vertically integrated thin film driving transistor in the backend storage region, thereby maintaining a vertical stacked memory cell structure with reduced lateral area [0016-0017]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by RIOS in combination with Lee in view of Juengling due to the above reason.
Regarding claim 15, Lee in view of Juengling teaches the PCRAM of claim 14, but does not teach wherein the second heating transistor includes a channel comprising an indium gallium zinc oxide composition.
RIOS teaches a vertically integrated resistive memory device (the 2T-1R memory cell integrated in backend layers between metal layers M1-M3, FIG. 8, [0015-0017, 0039-0040]) wherein the second heating transistor (the write transistor corresponding to the claimed the second heating transistor (the driving transistor) formed over common node N212, [0042]) includes a channel (IGZO channel layer 210 formed between common node/drain 212 and source 214, [0043]) comprising an indium gallium zinc oxide composition (210 is IGZO layer, [0043]).
As taught by RIOS, one of ordinary skill in the art would utilize and modify the above teaching into Lee in view of Juengling to obtain and achieve the PCRAM wherein the second heating transistor includes a channel comprising an indium gallium zinc oxide composition as claimed, because IGZO channel is suitable for forming a vertically integrated thin film driving transistor in the backend storage region, thereby maintaining a vertical stacked memory cell structure with reduced lateral area [0016-0017]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by RIOS in combination with Lee in view of Juengling due to the above reason.
Regarding claim 20, Lee teaches the PCRAM of claim 16, but does not teach the PCRAM further comprising: second heating transistors embedded in the dielectric layer disposed on the heating FETs and electrically connected with the regions of phase change material; wherein the second heating transistors includes channels comprising an indium gallium zinc oxide composition.
Juengling teaches a PCRAM (an array of cells 186 having phase-change memory element connected to source 192 or drain 194, FIGS. 24 and 27, [0005, 0043-0045, 0061]) further comprising: second heating transistors (upper transistor 188 formed by gates 180 and 182, FIG. 25, [0047]) embedded in the dielectric layer (a dielectric region including 156, 164, 178, and 184, extending from lower transistors 190 to and around 188, FIGS. 25-26, [0032, 0035, 0039, 0041, 0044]) disposed on the heating FETs (190) and electrically connected with the regions of phase change material (188 being in the current path to an phase-change memory element connected to source 192 or drain 194, [0050, 0061]).
As taught by Juengling, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM further comprising: second heating transistors embedded in the dielectric layer disposed on the heating FETs and electrically connected with the regions of phase change material as claimed, because vertically stacking and electrically isolating the transistors reduces lateral cell area while enabling both transistors to control the programming current passing through the phase-change material [0015-0017]. the transistors provides the functionality of a multi-transistor cell while reducing the lateral cell area compared with arranging the transistors side-by-side [0015-0017].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Juengling in combination with Lee due to the above reason.
Lee in view of Juengling does not teach the PCRAM wherein the second heating transistors includes channels comprising an indium gallium zinc oxide composition.
RIOS teaches a vertically integrated resistive memory device (the 2T-1R memory cell integrated in backend layers between metal layers M1-M3, FIG. 8, [0015-0017, 0039-0040]) wherein the second heating transistor (the write transistor corresponding to the claimed the second heating transistor (the driving transistor) formed over common node N212, [0042]) includes a channel (IGZO channel layer 210 formed between common node/drain 212 and source 214, [0043]) comprising an indium gallium zinc oxide composition (210 is IGZO layer, [0043]).
As taught by RIOS, one of ordinary skill in the art would utilize and modify the above teaching into Lee in view of Juengling to obtain and achieve the PCRAM wherein the second heating transistor includes a channel comprising an indium gallium zinc oxide composition as claimed, because IGZO channel is suitable for forming a vertically integrated thin film driving transistor in the backend storage region, thereby maintaining a vertical stacked memory cell structure with reduced lateral area [0016-0017]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by RIOS in combination with Lee in view of Juengling due to the above reason.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2007/0108433) in view of Mathew et al. (US 2009/0184306; hereinafter ‘Mathew’).
Regarding claim 4, Lee teaches the PCRAM of claim 1, but does not teach the PCRAM wherein the at least one heating FET is a finFET or a gate-all-around (GAA) FET.
Mathew teaches a PCRAM (10 comprising a completed phase change memory PCM cell including a phase change material PCMs, FIGS. 6-7, [0005, 0027]) wherein the at least one heating FET is a finFET or a GAA FET (the transistor is a FinFET and a silicide portion of fin 14 is used as the heater for the PCM cell, [0021, 0024]).
As taught by Mathew, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM wherein the at least one heating FET is a finFET or a GAA FET as claimed, because the fin shape provides pointed regions adjacent to the PCM region, thereby increasing current density and concentrating heat at the PCM region for more efficient heating [0023].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Mathew in combination with Lee due to the above reason.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2007/0108433) in view of Park et al. (US 2009/0085121; hereinafter ‘Park’).
Regarding claim 8, Lee teaches the PCRAM of claim 1, but does not teach the PCRAM further comprising: an oxide layer interposed between the wafer and the FET logic layer.
Park teaches a PCRAM (1000 including PCRAM, FIS. 10A, [0040, 0056]) further comprising: an oxide layer (1004, [0056]) interposed between the wafer and the FET logic layer (1004 interposed between underlying substrate/wafer and the silicon device layer in which the FinFET is formed, [0055-0056]).
As taught by Park, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM further comprising: an oxide layer interposed between the wafer and the FET logic layer as claimed, because forming FinFET on a silicon-on-insulator (SOI) substrate reduces capacitance and increase drive current capability [0055].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Lee due to the above reason.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2007/0108433) in view of Wu et al. (US 2014/0192592; hereinafter ‘Wu’).
Regarding claim 12, Lee teaches the PCRAM of claim 9, but does not teach the PCRAM wherein the chalcogenide material comprises a titanium antimony telluride (TST) composition.
Wu teaches a PCRAM (a phase change memory, [0004]) wherein the chalcogenide material comprises a TST composition (chalcogenide compounds used as the storage medium of the PCRAM comprises a Ti-SbTe3 phase-change memory material, [0040, 0092-0093]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM wherein the chalcogenide material comprises a TST composition as claimed, because TST improves thermal stability and data retention while reducing reset power consumption, thereby predictably improving PCRAM performance [0045-0046].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Lee due to the above reason.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2007/0108433) in view of Breitwisch et al. (US 2011/0057162; hereinafter ‘Breitwisch’).
Regarding claim 13, Lee teaches the PCRAM of claim 9 further comprising: an oxide layer (32 made of SiO2, FIG. 2, [0037, 0039]) interposed between the wafer and the FET logic layer (32 interposed between 10 and LL).
Lee does not teach that the oxide layer is a high density plasma (HDP) oxide layer.
Breitwisch teaches a PCRAM (150, FIG. 7A, [0024]) further comprising: a HDP oxide layer (110 is formed of high density plasma oxide, [0018]).
As taught by Breitwisch, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the PCRAM further comprising: a HDP oxide layer as claimed, because HDP oxide layer is suitable for filling exposed areas surrounding densely arranged device structures and for subsequent CMP planarization [0018].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Breitwisch in combination with Lee due to the above reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Lung et al. (US 2010/0295123) and Liu (US 2007/0268742) as a PCRAM structures having FETs electrically connected to a phase change material.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/18/26
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