DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/30/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over McGahay et al. (US 2011/0291279, cited on IDS) in view of Takemura et al. (US 2008/0258266).
a. Re claim 1, McGahay et al. disclose a method, comprising: forming a transistor (disclosed in [0019] but not shown) on a substrate 112 (see figs. 4-5E and related text; see remaining of disclosure for more details); forming an interconnect structure 114A (fig. 5B) on the transistor (note that 114A is on the substrate and therefore is on anything formed on the substrate including the transistors); depositing a dielectric layer on the interconnect structure 142 (or layer 114B; see fig. 5C); forming a metal ring structure 144 (in layer 114B; see [0027]); and forming a through-silicon via (TSV) 122&124 ([0022]) through a center of the metal ring structure. But McGahay et al. do not appear to explicitly disclose forming the metal ring structure comprising: etching the dielectric layer to form a ring-shaped opening to expose a portion of the interconnect structure through the ring-shaped opening, and depositing a conductive layer in the ring-shaped opening and on the exposed portion of the interconnect structure.
Nonetheless, McGahay et al. disclose that forming structure 114A-114C is done by conventional methods, which would implicitly mean for a skilled in the art methods comprising using a photoresist to pattern openings in dielectric layer 142 and filling the said openings with metallic materials to form structures 144. Takemura disclose in figs. 4A-5A and [0082]-[0091] the use of photoresist to pattern ring-shaped openings (105a&105c and 107a&107c) in dielectric layers (105 and 107), and subsequently filling the openings with metallic material (see [0033]) form ring structure (121&122, 123&124) similar to ring structures 144 in McGahay et al.
As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have performed the method of claim 1 such that forming the metal ring structure comprises etching the dielectric layer to form a ring-shaped opening to expose a portion of the interconnect structure through the ring-shaped opening (the opening in dielectric layer 142 of structure 114B would expose 114A in view of figs. 4A-C of Takumera et al. as applied in McGahay et al.), and depositing a conductive layer (layer 144 of 114B) in the ring-shaped opening and on the exposed portion of the interconnect structure, and all this as merely using a known-technique or something obvious to try to form a ring structure in a semiconductor device (see MPEP 2143.D&E).
b. Re claim 2, the method of claim 1, further comprises: depositing an other dielectric layer 142 (of structure 114C) on the metal ring structure; and etching an other ring-shaped opening in the other dielectric layer to expose a portion of the metal ring structure through the other ring-shaped opening (explicit as per claim 1 rejection above since the patterning and filling process is repeated).
c. Re claim 3, the method of claim 2, further comprises depositing an other conductive layer (144 of structure 114C) in the other ring-shaped opening and on the exposed portion of the metal ring structure.
d. Re claim 4, the method of claim 1, further comprises forming a metal via (144 in structure 114C or the lower narrower portion of 144 in structure 114C, noting that 144 or its lower narrower portion are basically via structures in the dielectric layer 142 of structure 114C) on the metal ring structure.
e. Re claim 5, it would have been obvious to one skilled in the art to have formed and additional structure 114D on structure 114C for a design requiring structures 114A-114D as implicitly suggested in [0027] (“The formation of BEOL wiring layer 114A and all subsequent BEOL wiring layers are by conventional methods. Additional BEOL wiring layers are formed until a predetermined number of BEOL wiring layers are formed to meet the design requirements of the semiconductor chip”). The modification would have resulted in having the method of claim 4, further comprising forming an other metal ring structure 144 (of structure 114D) on the metal via.
f. Re claim 6, forming the metal ring structure comprises forming the metal ring structure with a non-smooth inner surface (the inner sidewall surface of the metal ring 144 is not vertically straight but stepped, and as such it is a non-smooth inner surface).
g. Re claim 8, forming the TSV comprises etching a portion of the dielectric layer in the center of the metal ring structure (see fig. 5D and related text).
h. Re claim 9, forming the TSV comprises removing portions of the dielectric layer, the interconnect structure, and the substrate (see fig. 5D and related text).
i. Re claim 10, forming the TSV comprises: forming, at the center of the metal ring structure, an opening 116 (fig. 5D and related text) that extends into the substrate; depositing a barrier layer 124 in the opening (fig. 5D and related text); and depositing a metal layer 122 on the barrier layer (fig. 5D and related text).
j. Re claim 11, McGahay et al. disclose a method, comprising: forming device layer (layer formed of transistors disclosed in [0019] but not shown) on a substrate 112 (see figs. 4-5E and related text); depositing a dielectric layer 142 (of structure 114A or 114B; figs. 5B-C and related text) on the device layer; and forming, in the dielectric layer, a metal ring structure 144 with a non-smooth inner surface (the inner sidewall surface of a metal ring 144 is not vertically straight but stepped, and as such it is a non-smooth inner surface), comprising: forming a ring-shaped opening in the dielectric layer (opening in which 144 is formed; see also claim 1 rejection above as to forming such an opening); and depositing a conductive layer (material layer of 144) in the ring-shaped opening.
k. Re claim 12, the method of claim 11, further comprises forming a through-silicon via (TSV) 122&124 (figs. 5D-E and related text) through the dielectric layer and the device layer.
l. Re claim 13, the method of claim 11, further comprises: removing portions of the dielectric layer, the device layer, and the substrate to form an opening 116 (figs. 5D-E and related text); and depositing a metal layer 122 in the opening (figs. 5D-E and related text).
m. Re claim 14, method of claim 11, further comprises: forming, at a center of the metal ring structure, an opening 116 (figs. 5D-e and related text) that extends into the substrate; depositing a barrier layer 124 (figs. 5E-D and related text) in the opening; and depositing a metal layer 122 on the barrier layer.
n. Re claim 15, McGahay et Takemura et al. disclose all the limitations of claim 11 as stated above including depositing another conductive layer 144 (of structure 114C) on the metal layer, but do not appear to explicitly disclose the method of claim 11, wherein forming the metal ring structure further comprises: etching the conductive layer; and depositing an other conductive layer on the etched conductive layer. Takemura et al. rather disclose polishing the metal layer deposited in the opening in the dielectric layer (see fig. 4B and [0088]), but etching is a known alternative in the art to polishing for partially removing excess metallic layer after deposition. As such, and noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have etched the conductive layer instead of polishing it, and this as a non-inventive step of using a known alternative to polishing to achieve an expected result (see MPEP 2143.D&E). The modification would have resulted in the method of claim 11, wherein forming the metal ring structure further comprises: etching the conductive layer; and depositing an other conductive layer on the etched conductive layer.
o. Re claim 16, forming the metal ring structure further comprises: depositing an other dielectric layer 142 (of structure 114C) on the dielectric layer and the conductive layer; forming an other ring-shaped opening (opening in which 144 of structure 114C is laid in) in the other dielectric layer; and depositing an other conductive layer 144 (of structure 114C) in the other ring-shaped opening.
p. Re claim 17, McGahay et al. disclose a method, comprising: forming an interconnect structure 114A (fig. 5B and related text) on a semiconductor device (transistors formed in substrate 112 but not shown; see [0019]) on a substrate 112; depositing a dielectric layer 142 (of structure 114B) on the interconnect structure; etching the dielectric layer to form a ring-shaped opening with a non-smooth inner sidewall (see claim 1 rejection above as to the etching of dielectric layer; note that a sidewall surface of the opening is not vertically straight but stepped as can be seen in figs. 4A&4C of Takumera et al. and also in fig. 5B of McGahay when abstracting layer 144, and as such it is a non-smooth sidewall); and depositing a conductive layer 144 (of structure 114B) in the ring-shaped opening.
q. Re claim 18, the method of claim 17, further comprises: removing portions of the dielectric layer, the interconnect structure, and the substrate to form an opening 116 (fig. 5 D and related text). But McGahay et al. do not appear to explicitly disclose depositing a zirconium aluminum oxide layer in the opening, but rather an oxide (Tetraethyl orthosilicate (TEOS)) layer 118 ([0021] in the opening. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have used zirconium aluminum oxide layer instead of TEOS as a non-inventive step of using a known alternative material to TEOS for forming through-substrate electrode liners or isolators (see MPEP 2144.07).
r. Re claim 19, the method of claim 18, further comprises depositing a metal layer 122 on the zirconium aluminum oxide layer.
s. Re claim 20, the method of claim 17, further comprises: etching the conductive layer (see claim 15 rejection above as to the rationale for etching the conductive layer wherein such a rationale applies here); and depositing an other conductive layer 144 (of structure 114C) on the etched conductive layer.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kuo (US 2010/0140749) disclose a method of forming a structure similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
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