Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 7/30/24. Currently, claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 07/30/24, 10/09/24, 3/25/25, and 5/16/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15, and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PGPub 2022/0113502, hereinafter referred to as “Lee”).
Lee discloses the semiconductor method as claimed. See figures 1-24 and corresponding text, where Lee teaches, in claim 1, a semiconductor device comprising:
a first pad (MP1) over a semiconductor substrate (10W);
a second pad (MP2) adjacent to the first pad (MP1);
a first set of dummy pads (DPR1) at least partially between the first pad (MP1) and the second pad (MP2); and
a bonding dielectric material (10UI) over the first pad (MP1), the second pad (MP2), and the first set of dummy pads (DPR1). (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 2, wherein the first set of dummy pads comprises first dummy pads and second dummy pads between the first pad and the second pad, the second dummy pads having a larger width than the first dummy pads. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 3, wherein the second dummy pads have a larger width than a distance between the first pad and the second pad. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 4, wherein the second dummy pads have chamfered corners. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 5, wherein the first set of dummy pads comprises a third dummy pad adjacent to one of the second dummy pads, the third dummy pad being a continuous line. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 6, wherein the first set of dummy pads comprises a third dummy pad adjacent to one of the second dummy pads, the third dummy pad being a discontinuous line. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 7, a semiconductor device comprising: (figures 8; [0042-0044], [0053], [0063-0070])
a first pad and a second pad over a metallization layer;
a first set of dummy pads around the first pad and the second pad, the first set of dummy pads comprising:
a first dummy pad between the first pad and the second pad, the first dummy pad being rectangular in shape;
a second dummy pad between the first pad and the second pad, the second dummy pad being wider than the first dummy pad;
a third dummy pad on an opposite side of the second dummy pad from the first dummy pad, the third dummy pad having a different width than the second dummy pad; and
a bonding layer over the first pad and the second pad, the bonding layer comprising a conductive bond pad in electrical connection with the first pad.
Lee teaches, in claim 8, wherein the bonding layer is bonded to a second bonding layer. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 9, wherein the bonding layer is bonded to the second bonding layer with a hybrid bond. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 10, wherein the bonding layer is bonded to the second bonding layer with a fusion bond. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 11, wherein the third dummy pad is discontinuous. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 12, wherein different portions of the third dummy pad have centerlines that are off-center from each other. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 13, wherein the second dummy pad has a first chamfered corner. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 14, wherein the first pad has a second chamfered corner. (figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 15, a semiconductor device comprising: (figures 8; [0042-0044], [0053], [0063-0070])
metallization layers over a semiconductor substrate;
a first pad separated from a second pad over the metallization layers;
a first dummy pad between the first pad and the second pad; and
a second dummy pad at least partially between the first pad and the second pad, the second dummy pad having a width larger than a shortest distance between the first pad and the second pad. figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 18, wherein the second dummy pad has at least one chamfered corner. figures 8; [0042-0044], [0053], [0063-0070])
Lee teaches, in claim 19, further comprising a third dummy pad on an opposite side of the second dummy pad from the first dummy pad, the third dummy pad being discontinuous.
20. The semiconductor device of claim 15, wherein the first pad is circular figures 8; [0042-0044], [0053], [0063-0070])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPub 2022/0013502, hereinafter referred to as “Lee”) as applied to claim 21 above, and further in view of Lee et al. (US PGPub 2022/0013502, hereinafter referred to as “Lee”).
Lee discloses the semiconductor method of claim 7 above.
However, Lee fails to show, in claim 16, wherein the second dummy pad is in an "S"- shape.
Lee teaches, in claim 16, that the dummy pads can be made in various shapes [0044], and provides the advantages of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations ([0003-0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate, wherein the second dummy pad is in an "S"- shape, in the method of Lee, according to the teachings of Lee, with the motivation of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations
Lee fails to explicitly show, in claim 20, wherein the first pad and the second pad have a pitch of about 35 µm.
Lee teaches, in claim 20, that the main connection pad structures having different pitches ([0041], [0068]). In addition, Lee provides the advantages of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations ([0003-0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein the first pad and the second pad have a pitch of about 35 µm, in the method of Lee, according to the teachings of Lee, with the motivation of preventing local erosion of insulating layers surrounding connection pads, thus improving bonding operations
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STANETTA D ISAAC/ Examiner, Art Unit 2898 July 25, 2026
Prosecution Insights