Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made that the instant application is a continuation of US Patent application 18523553; US Patent application 18523553 is a continuation of US Patent application 17854683 and US Patent application 17854683 is divisional of US Patend application 16573630.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(2):
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 15 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jacobs et al. (US 20190237418 A1 - hereinafter Jacobs).
Regarding Claim 15, Jacobs teaches a method of manufacturing a semiconductor device (see the entire document; Fig. 2 in view of Fig. 1; specifically, [0023]-[0032], and as cited below), comprising:
forming a layer of active devices on a semiconductor substrate (Fig. 1 and [0023] teach IC die 114 includes a logic die which inherently incldues active devices on a substrate); and
forming a metallization layer (Coaxial Interconnect(s) 116 – Fig. 1 – [0029]) over the layer of active devices (active devices of 114), the metallization layer comprising:
a signal connector (214 – Fig. 2 – [0032]);
a first power grid line (216 – [0032]); and
a dielectric encasing (218 – [0032]) the signal connector (214) and extending from the signal connector (214) in each direction parallel with the semiconductor substrate to make contact with the first power grid line (216).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jacobs in view of Nishizawa et al. (US 20130181727 A1 – hereinafter Nishizawa).
Regarding Claim 1, Jacobs teaches a method of manufacturing a semiconductor device (see the entire document; Fig. 2 in view of Fig. 1; specifically, [0029]-[0032], and as cited below), comprising:
forming a first metallization layer (Coaxial Interconnect(s) 116 – Fig. 1 – [0029]) over a substrate (206 – Fig. 2 – [0031], the first metallization layer (116) comprising:
a signal connector portion (214 – Fig. 2 – [0032]); and
a first power grid line (216 – [0032]) extending parallel with a major surface (top surface) of the substrate (206), the first power grid line (216) surrounding the signal connector portion in a top down view (bottom figure of Fig.2 shows 216 surrounds 214); and
forming a bond pad metal trace (204 – [0030) in electrical connection with the signal connector portion (214).
But Jacobs as applied above does not expressly disclose forming a bond pad metal trace after forming the first metallization layer.
However, it is well known in the art to form a bond pad metal trace after the forming of a metallization layer as is also taught by Nishizawa (Nishizawa teaches in Fig. 1 and [0066] that a connecting pad 5 is formed after forming a metallization layer 7).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of forming a bond pad metal trace after forming the first metallization layer as taught by Nishizawa into Jacobs.
An ordinary artisan would have been motivated to integrate Nishizawa structure into Jacobs structure in the manner set forth above for, at least, this integration will provide a connection pad formed to connect the signal line to outside as is well known in the art.
Allowable Subject Matter
Claims 2-7, 16-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The method of claim 1, wherein the forming the first metallization layer further comprises forming a second power grid line parallel with the first power grid line, wherein sides of the first power grid line and sides of the second power grid line are coterminus.
Claim 3 depends from claim 2.
Regarding claim 4: The method of claim 1, wherein the forming the first metallization layer further comprises forming a second power grid line parallel with the first power grid line, wherein sides of the first power grid line are offset from sides of the second power grid line.
Claims 5-7 depend from claim 4
Regarding claim 16: The method of claim 15, further comprising: depositing a dielectric layer over the metallization layer; and forming a via to the signal connector.
Claim 17 depends from claim 16.
Regarding claim 18: The method of claim 15, wherein the metallization layer further comprises a second power grid line, and wherein the second power grid line has sidewalls that are coterminus with the first power grid line.
Regarding claim 19: The method of claim 15, wherein the metallization layer further comprises a second power grid line, and wherein the second power grid line has sidewalls that are mis-aligned with the first power grid line.
Claim 20 depends from claim 19.
REASON FOR ALLOWANCE
Claims 8-14 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 8, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20190237418 A1 to Jacobs) substantially teach(es) some of limitations in claim 8 as indicated in the rejection of claim 15, but not the limitations of “forming a first opening through a dielectric material to expose a signal connector; forming a second opening through the dielectric material to expose a first power line that extends parallel with a top surface of the dielectric material” as recited in claim 15. Therefore, claim 15 is deemed patentable over the prior art.
Regarding claims 9-14, they are allowed due to their dependencies on claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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