DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-11, 14, 16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 10,410,916 to Hong et al. (hereinafter Hong).
With respect to claim 10, Hong discloses a structure (e.g., air-gap-containing interconnect structure) (Hong, Fig. 20, Col. 1-12) comprising:
a first conductive feature (11) (Hong, Fig. 20, Col. 3, lines 1-23; Col. 11, lines 58-61) over the substrate (10);
a second conductive feature (e.g., Va/Wa including conductive part 25v/25a and diffusion prevention pattern 23v/23a) (Hong, Fig. 20, Col. 3, lines 62-67; Col. 4, lines 1-17; Col. 11, lines 58-61) over and electrically coupling to the first conductive feature (11), wherein the second conductive feature (Va/Wa) comprises:
a diffusion barrier (23v/23a) (Hong, Fig. 20, Col. 4, lines 1-17); and
a metallic material (25v/25a) (Hong, Fig. 20, Col. 4, lines 3-11) in a basin formed by the diffusion barrier (23v/23a);
an air spacer (Av1/Aw1 and Av2/Aw2) (Hong, Fig. 20, Col. 5, lines 3-11; Col. 12, lines 6-9) encircling a top portion of the second conductive feature (Va/Wa); and
a dielectric layer (13/15) (Hong, Fig. 20, Col. 3, lines 24-29; Col. 12, lines 6-9) encircling the air spacer (Av1/Aw1 and Av2/Aw2), wherein the dielectric layer (13/15) comprises a high-k dielectric material (13, SiN) that comprises nitrogen.
Regarding claim 11, Hong discloses the structure of claim 10. Further, Hong discloses the structure further comprising a spacer layer (18v1/18v2) (Hong, Fig. 20, Col. 4, lines 40-44; Col. 10, lines 66-67; Col. 11, lines 1-2; lines 62-67; Col. 12, lines 1-10) separating a bottom portion of the second conductive feature (Va/Wa) from the dielectric layer (13/15), wherein the spacer layer (18v1/18v2) is directly underlying and exposed to the air spacer (Av1/Aw1 and Av2/Aw2).
Regarding claim 14, Hong discloses the structure of claim 11. Further, Hong discloses the structure, wherein the spacer layer (18v1/18v2) comprises silicon (SiN) (Hong, Fig. 20, Col. 4, lines 40-44; Col. 10, lines 66-67; Col. 11, lines 1-2; lines 62-67; Col. 12, lines 1-10).
With respect to claim 16, Hong discloses a structure (e.g., air-gap-containing interconnect structure) (Hong, Figs. 1, 20, Cols. 1-5, Cols. 11-12) comprising:
a first dielectric layer (3) (Hong, Figs. 1, 20, Col. 3, lines 16-23);
a first etch stop layer (13) (Hong, Figs. 1, 20, Col. 3, lines 24-27) over the first dielectric layer (3);
a second dielectric layer (15) (Hong, Figs. 1, 20, Col. 3, lines 24-29) over the first etch stop layer (13);
a conductive feature (Va/Wa) (Hong, Figs. 1, 20, Col. 3, lines 62-67; Col. 4, lines 1-17) in the second dielectric layer (15) and the first etch stop layer (13);
an air gap (Av1/Av2 and Aw1/Aw2) (Hong, Figs. 1, 20, Col. 4, lines 59-67; Col. 5, lines 1-20) in the second dielectric layer (15) and the first etch stop layer (13), wherein the air gap comprises a first portion (Av1/Aw1) and a second portion (Av2/Aw2) on opposing sides of the conductive feature (Va/Wa);
a metal cap (27) (Hong, Figs. 1, 20, Col. 5, lines 36-38) over and contacting the conductive feature (Va/Wa); and
a second etch stop layer (29) (Hong, Figs. 1, 20, Col. 5, lines 38-41) over and contacting the metal cap (27) and the conductive feature (Va/Wa).
Regarding claim 20, Hong discloses the structure of claim 16. Further, Hong discloses the structure further comprising a spacer layer (18v1/18v2) (Hong, Fig. 20, Col. 4, lines 40-44; Col. 10, lines 66-67; Col. 11, lines 1-2; lines 62-67; Col. 12, lines 1-10) between the conductive feature (Va/Wa) and the second dielectric layer (15), wherein the spacer layer (18v1/18v2) is directly underlying and exposed to the air gap (Av1/Av2), and the spacer layer (18v1/18v2) is at a position higher than the first dielectric layer (3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0030128 to Bu et al. (hereinafter Bu) in view of Choi et al. (US 2003/0209805, hereinafter Choi) and Lu e al. (US 2016/0093668, hereinafter Lu).
With respect to claim 1, Bu discloses a structure (e.g., air-gap-containing interconnect structure) (Bu, Fig. 1L, ¶0002, ¶0016-¶0017, ¶0027-¶0053) comprising:
a substrate (10) (Bu, Fig. 1L, ¶0028-¶0029);
a first conductive feature (22) (Bu, Fig. 1L, ¶0031) over the substrate (10);
a first etch stop layer (26) (Bu, Fig. 1L, ¶0032) over the first conductive feature (22);
a dielectric layer (30) (Bu, Fig. 1L, ¶0033) over the first etch stop layer (26),
a second conductive feature (44/40) (Bu, Fig. 1L, ¶0039-¶0040) in the dielectric layer (30) and the first etch stop layer (26), wherein the second conductive feature (44/40) is over and contacting the first conductive feature (22);
an air spacer (45) (Bu, Fig. 1L, ¶0042) encircling the second conductive feature (44/40), wherein sidewalls of the second conductive feature (44/40) are exposed to the air spacer (45); and
a second etch stop layer (50) (Bu, Fig. 1L, ¶0043) over and contacting the dielectric layer (30), wherein the second etch stop layer (50) is further over the second conductive feature (44/40).
Further, Bu does not specifically disclose that (1) the dielectric layer comprises nitrogen therein, wherein (2) the dielectric layer comprises a high-k dielectric material.
Regarding (1), Choi teaches forming semiconductor integrated circuit (Choi, Fig. 6, ¶0002, ¶0014-¶0029) comprising nitrogen containing silicon oxide film (e.g., 120) having a low dielectric constant in a range between 3.2 and 3.7 (Choi, Fig. 6, ¶0014, ¶0019, ¶0021-¶0022, ¶0025), and utilizing a nitrogen containing gas to incorporate nitrogen into silicon oxide film to obtain excellent moisture resistance to improve film stability and to provide a good adhesion to the metal surfaces (Choi, Fig. 6, ¶0014, ¶0019, ¶0021-¶0022, ¶0029).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu by forming low-k nitrogen containing silicon oxide film as taught by Choi to have the structure, wherein the dielectric layer comprises nitrogen therein, in order to provide a dielectric layer having an excellent moisture resistance to improve film stability, and a good adhesion to the metal surfaces (Choi, ¶0014, ¶0019, ¶0021-¶0022, ¶0029).
Regarding (2), Lu teaches forming semiconductor integrated circuit (Lu, Fig. 5K, ¶0010, ¶0028-¶0029, ¶0054-¶0063) comprising an interconnect structure having improved mechanical stability and reduced parasitic capacitance, wherein the interlayer dielectric layer (IMD2/IMD3) including a via structure/metal line (508l/530) comprises high-k dielectric layer (e.g., 508c (IMD3)) to achieve high rigidity and mechanical stability, and low-k dielectric layer (e.g., 508i (IMD2)) to provide low parasitic capacitance (Lu, ¶0010, ¶0032, ¶0055, ¶0059, ¶0063).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu by forming an interlayer dielectric layer including high-k dielectric layer and low-k dielectric layer as taught by Lu to have the structure, wherein the dielectric layer comprises a high-k dielectric material, in order to achieve high rigidity and mechanical stability, and thus to obtain an interconnect structure having improved mechanical stability and reduced parasitic capacitance (Lu, ¶0010, ¶0032, ¶0055, ¶0059, ¶0063).
Regarding claim 3, Bu in view of Choi and Lu discloses the structure of claim 1. Further, Bu discloses the structure, wherein the air spacer (45) (Bu, Fig. 1L, ¶0042) extends from a top surface of the dielectric layer (30) to a bottom surface of the first etch stop layer (26).
Regarding claim 6, Bu in view of Choi and Lu discloses the structure of claim 1. Further Bu discloses the structure, wherein no dielectric material is between the second conductive feature (44/40) (Bu, Fig. 1L, ¶0039-¶0040, ¶0042) and the air spacer (45).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0030128 to Bu in view of Choi (US 2003/0209805) and Lu (US 2016/0093668) as applied to claim 1, and further in view of Lee et al. (US 2017/0263549, hereinafter Lee’549).
Regarding claim 2, Bu in view of Choi and Lu discloses the structure of claim 1. Further, Bu does not specifically disclose the structure, wherein the dielectric layer comprises a top portion and a bottom portion, wherein the top portion has a greater nitrogen atomic percentage than the bottom portion.
However, Lee’549 teaches forming an interconnection structure (Lee’549, Figs. 1A-1G, ¶0003, ¶0011-¶0046, ¶0048) including a dielectric layer to form reliable semiconductor device, wherein the dielectric layer (106) comprises a bottom portion (106L) (Lee’549, Figs. 1A-1G, ¶0036, ¶0040) having a first nitrogen concentration and an upper portion (106U) over the lower portion (106L), wherein the upper portion (106U) contains a second nitrogen concentration greater than that of the bottom portion (106L), to protect the dielectric layer from being damaged during subsequent processes to improve quality and reliability of the interconnection structure (Lee’549, ¶0003, ¶0040, ¶0046, ¶0048).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu/Choi/Lu by forming the dielectric layer including greater nitrogen concentration in the top portion as taught by Lee’549 to have the structure, wherein the dielectric layer comprises a top portion and a bottom portion, wherein the top portion has a greater nitrogen atomic percentage than the bottom portion, in order to provide protection of the dielectric layer from being damaged during subsequent processes to improve quality and reliability of the interconnection structure (Lee’549, ¶0003, ¶0040, ¶0046, ¶0048).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0030128 to Bu in view of Choi (US 2003/0209805) and Lu (US 2016/0093668) as applied to claim 1, and further in view of Chen et al. (US 2007/0205516, hereinafter Chen).
Regarding claim 4, Bu in view of Choi and Lu discloses the structure of claim 1. Further Bu does not specifically disclose the structure, wherein the dielectric layer has a hardness in a range between about 15 GPa and about 35 GPa.
However, Chen teaches forming an interconnect structure (Chen, Figs. 1A-1B, 2, ¶0006-¶0008, ¶0017-¶0030) comprising plug/wiring in a low-k dielectric layer (120) including sub-layers (21/23) having a hardness in a range between 0.1 and 49 GPa (Chen, Figs. 1A-1B, 2, ¶0018) and the hardened sub-layer (22) having hardness in a range between 0.5 and 50 GPa, to prevent deformation of the low-k dielectric layer and peel-off of the interconnection form the low-k dielectric layer is prevented thereby improving yield and reliability of the semiconductor device (Chen, ¶0006, ¶0018, ¶0022-¶0023, ¶0030).
The claimed range lies inside the range of Chen. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu/Choi/Lu by forming the low-k dielectric layer having specific hardness as taught by Chen to have the structure, wherein the dielectric layer has a hardness in a range between about 15 GPa and about 35 GPa, in order to provide protection of the dielectric layer from being damaged during subsequent processes to improve quality and reliability of the interconnection structure (Lee’549, ¶0003, ¶0040, ¶0046, ¶0048).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0030128 to Bu in view of Choi (US 2003/0209805) and Lu (US 2016/0093668) as applied to claim 1, and further in view of Filippi et al. (US Patent No. 7,560,375, hereinafter Filippi).
Regarding claim 5, Bu in view of Choi and Lu discloses the structure of claim 1. Further Bu does not specifically disclose the structure further comprising a dielectric material contacting a sidewall of a bottom portion of the second conductive feature, wherein a top portion of the second conductive feature is exposed to the air spacer, and wherein the dielectric material and the dielectric layer are formed of different materials.
However, Filippi teaches forming the semiconductor structure (Filippi, Figs. 6-7, Col. 1, lines 13-21; Col. 2, lines 7-20; Col. 3, lines 11-62; Col. 4, lines 42-48) comprising air spacers, wherein a sacrificial layer (150) is formed in the opening (132) of the dielectric layer (120) to form sacrificial spacer layer (160) including a dielectric material (e.g., SiO2) contacting a sidewall of a bottom portion (138) of the second conductive feature (137/138), wherein a top portion (137) of the second conductive feature is exposed to the air spacer (190), and wherein the dielectric material (160, SiO2) and the dielectric layer (120, low-k material) are formed of different materials, to provide damascene wire formation process to reduce capacitive coupling and to improve structural stability (Filippi, Col. 1, lines 13-21; Col. 2, lines 7-20; Col. 4, lines 42-48).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu/Choi/Lu by forming the semiconductor structure including air gaps in the damascene wire formation process as taught by Filippi to have the structure, further comprising a dielectric material contacting a sidewall of a bottom portion of the second conductive feature, wherein a top portion of the second conductive feature is exposed to the air spacer, and wherein the dielectric material and the dielectric layer are formed of different materials, in order to provide an improved method to form an interconnect structure with reduced capacitive coupling and improved structural stability (Filippi, Col. 1, lines 13-21; Col. 2, lines 7-20; Col. 4, lines 42-48).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0030128 to Bu in view of Choi (US 2003/0209805) and Lu (US 2016/0093668) as applied to claim 1, and further in view of Hong (US Patent No. 10,410,916).
Regarding claim 7, Bu in view of Choi and Lu discloses the structure of claim 1. Further, Bu does not specifically disclose the structure further comprising a metal cap over the second conductive feature, wherein the second etch stop layer is over and is in contact with the metal cap.
However, Hong teaches forming a semiconductor structure (Hong, Fig. 1, Col. 1, lines 32-51; Cols. 3-5) comprising a second conductive feature (e.g., via plug 25a/23a) and a metal cap (e.g., 27, cobalt or cobalt silicide) (Hong, Fig. 1, Col. 5, lines 36-44) over the second conductive feature (25a/23a), wherein the second etch stop layer (29) is over and is in contact with the metal cap (27), to provide protection of the via plug, and thus to obtain a multi-level wiring structure for high speed operation, high density and low power consumption.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu/Choi/Lu by forming a metal cap as taught by Hong to have the structure further comprising a metal cap over the second conductive feature, wherein the second etch stop layer is over and is in contact with the metal cap, in order to increase the contact area of the conductive structure to improve contact resistance, and to provide protection of the via plug, and thus to obtain a multi-level wiring structure for high-speed operation, high density and low power consumption (Hong, Col. 1, lines 14-22, lines 32-51; Col. 5, lines 36-44).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0030128 to Bu in view of Choi (US 2003/0209805), Lu (US 2016/0093668, and Hong (US Patent No. 10,410,916) as applied to claim 7, and further in view of Lee et al. (US 2014/0308794, hereinafter Lee).
Regarding claims 8 and 9, Bu in view of Choi, Lu, and Hong discloses the structure of claim 7. Further, Bu does not specifically disclose the structure, wherein an extension portion of the metal cap is lower than a top surface of the second conductive feature (as claimed in claim 8); wherein the extension portion of the metal cap contacts a sidewall of the second conductive feature (as claimed in claim 9).
However, Lee teaches forming a metal capping layer (108/23A) (Lee, Figs. 1A-1B, 3A-3B, ¶0007-¶0012, ¶0043-¶0057, ¶0075-¶0076) over the conductive feature (105/107), wherein the metal capping layer (108/23A) comprises an extension portion extending into the air spacer (110), such that an extension portion of the metal cap (108/23A) is lower than a top surface of the second conductive feature (105/107), and the extension portion of the metal cap (108/23A) contacts a sidewall of the second conductive feature (105/107), to increase the contact area of the conductive structure (106/107) to improve contact resistance (Lee, Figs. 1A-1B, 3A-3B, ¶0050, ¶0054). In Lee, the air gap (110) is stably capped with the metal layer (108) to improve insulating characteristics of the conductive structure, and to reduce parasitic capacitance between adjacent conductive structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Bu/Choi/Lu/Hong by capping the air gaps with the conductive layer as taught by Lee to have the structure, wherein an extension portion of the metal cap is lower than a top surface of the second conductive feature (as claimed in claim 8); wherein the extension portion of the metal cap contacts a sidewall of the second conductive feature (as claimed in claim 9), in order to increase the contact area of the conductive structure to improve contact resistance, and to improve insulating characteristics of the conductive structure and to reduce parasitic capacitance between adjacent conductive structures (Lee, ¶0006, ¶0007, ¶0050, ¶0054).
Claims 10-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/044865 to Chen et al. (hereinafter Chen’865) in view of Wong (US 2002/0074663).
With respect to claim 10, Chen’865 discloses a structure (e.g., air-gap-containing interconnect structure) (Chen’865, Fig. 1, ¶0014-¶0027) comprising:
a first conductive feature (120b, via region) (Chen’865, Fig. 1, ¶0019, ¶0024) over the substrate (101);
a second conductive feature (e.g., 120a, metal line) (Chen’865, Fig. 1, ¶0019, ¶0024) over and electrically coupling to the first conductive feature (120b), wherein the second conductive feature (120a) comprises:
a diffusion barrier (e.g., TaN or TiN) (Chen’865, Fig. 1, ¶0020); and
a metallic material (e.g., copper) (Chen’865, Fig. 1, ¶0019) in a basin formed by the diffusion barrier (e.g., barrier layer on sidewalls and bottom of the interconnect 120a);
an air spacer (140a) (Chen’865, Fig. 1, ¶0022) encircling a top portion of the second conductive feature (120a); and
a dielectric layer (110) (Chen’865, Fig. 1, ¶0017, ¶0022) encircling the air spacer (140a), wherein the dielectric layer (110) comprises a dielectric material (110, carbon-containing silicon nitride) that comprises nitrogen.
Further, Chen’865 does not specifically disclose that the dielectric layer comprises a high-k dielectric material that comprises nitrogen.
However, Wong teaches forming an interconnect structure (Wong, Fig. 10, ¶0022-¶0052), wherein a second conductive feature (204/206) is formed in a dielectric layer (109/110 and 112), wherein the dielectric layer (109/110) comprises a high-k dielectric material (e.g., 109/110 of SiN) (Wong, Fig. 10, ¶0048) that comprises nitrogen, to provide structural support and mechanical reinforcement for low dielectric constant insulator on integrated circuits.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Chen’865 by forming a dielectric layer comprising low-k and high-k dielectric materials as taught by Wong to have the structure, wherein the dielectric layer comprises a high-k dielectric material that comprises nitrogen, in order to provide structural support and mechanical reinforcement for low dielectric constant insulator on integrated circuit (Wong, ¶0050-¶0052).
Regarding claim 11, Chen’865 in view of Wong discloses the structure of claim 10. Further, Chen’865 discloses the structure further comprising a spacer layer (130a/150a) (Chen’865, Fig. 1, ¶0021, ¶0024-¶0025) separating a bottom portion of the second conductive feature (120a) from the dielectric layer (110), wherein the spacer layer (150a) is directly underlying and exposed to the air spacer (140a).
Regarding claim 14, Chen’865 in view of Wong discloses the structure of claim 11. Further, Chen’865 discloses the structure, wherein the spacer layer (130a/150a) (Chen’865, Fig. 1, ¶0021, ¶0024-¶0025) comprises silicon.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,410,916 to Hong in view of King et al. (US 2013/0292835, hereinafter King).
Regarding claims 12-13, Hong discloses the structure of claim 11. Further, Hong does not specifically disclose the structure, wherein the spacer layer comprises a metal oxide (as claimed in claim 12); wherein the metal oxide comprises titanium oxide or aluminum oxide (as claimed in claim 13).
However, King teaches forming an interconnect structure (205) (King, Fig. 2G, ¶0001, ¶0004, ¶0014-¶0034) comprising metal structures in the low-k dielectric layer (210) including air gaps (255), and further including a spacer layer (e.g., 240, a dielectric diffusion barrier as a contiguous liner) (King, Fig. 2G, ¶0023-¶0027, ¶0031) including a relatively high dielectric constant material, such as aluminum oxide, titanium oxide, or a silicon alloy of metal oxide, to provide a dense film having high conformality and capable of providing hermiticity at the minimum thickness to prevent out-diffusion of metal (e.g., Cu) from the metal interconnect into the surrounding dielectric layer, and to prevent moisture and wet chemical in-diffusion from the dielectric layer or from air-gaps into the metal interconnect.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Hong by forming a spacer layer as a dielectric diffusion barrier liner of King to have the structure, wherein the spacer layer comprises a metal oxide (as claimed in claim 12); wherein the metal oxide comprises titanium oxide or aluminum oxide (as claimed in claim 13), in order to provide a dense film having high conformality and capable of providing hermiticity at the minimum thickness to prevent out-diffusion of metal (e.g., Cu) from the metal interconnect into the surrounding dielectric layer, and to prevent moisture and wet chemical in-diffusion from the dielectric layer or from air-gaps into the metal interconnect (King, ¶0004, ¶0023-¶0027, ¶0031).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/044865 to Chen’865 in view of Wong (US 2002/0074663) as applied to claim 11, and further in view of King (US 2013/0292835).
Regarding claims 12-13, Chen’865 in view of Wong discloses the structure of claim 11. Further, Chen’865does not specifically disclose the structure, wherein the spacer layer comprises a metal oxide (as claimed in claim 12); wherein the metal oxide comprises titanium oxide or aluminum oxide (as claimed in claim 13).
However, King teaches forming an interconnect structure (205) (King, Fig. 2G, ¶0001, ¶0004, ¶0014-¶0034) comprising metal structures in the low-k dielectric layer (210) including air gaps (255), and further including a spacer layer (e.g., 240, a dielectric diffusion barrier as a contiguous liner) (King, Fig. 2G, ¶0023-¶0027, ¶0031) including a relatively high dielectric constant material, such as aluminum oxide, titanium oxide, or a silicon alloy of metal oxide, to provide a dense film having high conformality and capable of providing hermiticity at the minimum thickness to prevent out-diffusion of metal (e.g., Cu) from the metal interconnect into the surrounding dielectric layer, and to prevent moisture and wet chemical in-diffusion from the dielectric layer or from air-gaps into the metal interconnect.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Chen’865/Wong by forming a spacer layer as a dielectric diffusion barrier liner of King to have the structure, wherein the spacer layer comprises a metal oxide (as claimed in claim 12); wherein the metal oxide comprises titanium oxide or aluminum oxide (as claimed in claim 13), in order to provide a dense film having high conformality and capable of providing hermiticity at the minimum thickness to prevent out-diffusion of metal (e.g., Cu) from the metal interconnect into the surrounding dielectric layer, and to prevent moisture and wet chemical in-diffusion from the dielectric layer or from air-gaps into the metal interconnect (King, ¶0004, ¶0023-¶0027, ¶0031).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,410,916 to Hong in view of Chen (US 2007/0205516).
Regarding claim 15, Hong discloses the structure of claim 1. Further, Hong does not specifically disclose the structure, wherein the dielectric layer has a hardness in a range between about 15 GPa and about 35 GPa.
However, Chen teaches forming an interconnect structure (Chen, Figs. 1A-1B, 2, ¶0006-¶0008, ¶0017-¶0030) comprising plug/wiring in a low-k dielectric layer (120) including sub-layers (21/23) having a hardness in a range between 0.1 and 49 GPa (Chen, Figs. 1A-1B, 2, ¶0018) and the hardened sub-layer (22) having hardness in a range between 0.5 and 50 GPa, to prevent deformation of the low-k dielectric layer and peel-off of the interconnection form the low-k dielectric layer is prevented thereby improving yield and reliability of the semiconductor device (Chen, ¶0006, ¶0018, ¶0022-¶0023, ¶0030).
The claimed range lies inside the range of Chen. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Hong by forming the low-k dielectric layer having specific hardness as taught by Chen to have the structure, wherein the dielectric layer has a hardness in a range between about 15 GPa and about 35 GPa, in order to provide protection of the dielectric layer from being damaged during subsequent processes to improve quality and reliability of the interconnection structure (Lee’549, ¶0003, ¶0040, ¶0046, ¶0048).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2015/044865 to Chen’865 in view of Wong (US 2002/0074663) as applied to claim 10, and further in view of Chen (US 2007/0205516).
Regarding claim 15, Chen’865 in view of Wong discloses the structure of claim 1. Further, Chen’865 does not specifically disclose the structure, wherein the dielectric layer has a hardness in a range between about 15 GPa and about 35 GPa.
However, Chen teaches forming an interconnect structure (Chen, Figs. 1A-1B, 2, ¶0006-¶0008, ¶0017-¶0030) comprising plug/wiring in a low-k dielectric layer (120) including sub-layers (21/23) having a hardness in a range between 0.1 and 49 GPa (Chen, Figs. 1A-1B, 2, ¶0018) and the hardened sub-layer (22) having hardness in a range between 0.5 and 50 GPa, to prevent deformation of the low-k dielectric layer and peel-off of the interconnection form the low-k dielectric layer is prevented thereby improving yield and reliability of the semiconductor device (Chen, ¶0006, ¶0018, ¶0022-¶0023, ¶0030).
The claimed range lies inside the range of Chen. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Chen’865/Wong by forming the low-k dielectric layer having specific hardness as taught by Chen to have the structure, wherein the dielectric layer has a hardness in a range between about 15 GPa and about 35 GPa, in order to provide protection of the dielectric layer from being damaged during subsequent processes to improve quality and reliability of the interconnection structure (Lee’549, ¶0003, ¶0040, ¶0046, ¶0048).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,410,916 to Hong in view of Lee (US 2014/0308794).
Regarding claims 17 and 18, Hong discloses the structure of claim 16. Further, Hong does not specifically disclose the structure, wherein the metal cap comprises an extension portion in the air gap (as claimed in claim 17); wherein the extension portion of the metal cap contacts a sidewall of the conductive feature (as claimed in claim 18).
However, Lee teaches forming a metal capping layer (108/23A) (Lee, Figs. 1A-1B, 3A-3B, ¶0007-¶0012, ¶0043-¶0057, ¶0075-¶0076) over the conductive feature (105/107), wherein the metal capping layer (108/23A) comprises an extension portion extending into the air spacer (110), such that an extension portion of the metal cap (108/23A) is lower than a top surface of the second conductive feature (105/107), and the extension portion of the metal cap (108/23A) contacts a sidewall of the second conductive feature (105/107), to increase the contact area of the conductive structure (106/107) to improve contact resistance (Lee, Figs. 1A-1B, 3A-3B, ¶0050, ¶0054). In Lee, the air gap (110) is stably capped with the metal layer (108) to improve insulating characteristics of the conductive structure, and to reduce parasitic capacitance between adjacent conductive structures.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Hong by capping the air gaps with the conductive layer as taught by Lee to have the structure, wherein the metal cap comprises an extension portion in the air gap (as claimed in claim 17); wherein the extension portion of the metal cap contacts a sidewall of the conductive feature (as claimed in claim 18), in order to increase the contact area of the conductive structure to improve contact resistance, and to improve insulating characteristics of the conductive structure and to reduce parasitic capacitance between adjacent conductive structures (Lee, ¶0006, ¶0007, ¶0050, ¶0054).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,410,916 to Hong in view of Dubin et al. (US Patent No. 7,586,196, hereinafter Dubin).
Regarding claim 19, Hong discloses the structure of claim 16. Further, Hong does not specifically disclose the structure, wherein the metal cap physically contacts the second dielectric layer.
However, Dubin teaches forming an interconnect structure comprising a metal cap (240, Co or Ni metal material) as a protection layer over the interconnect (236) and the air gap (246), wherein the metal cap (240) physically contacts the second dielectric layer (244), to reduce the incidence of diffusion and electromigration to provide improved air-gap interconnection structure (Dubin, Col. Lines 13-15; Col. 2, lines 53-67; Col. 3, lines 119; Col. 4, line 50-67; Col. 5, lines 1-60).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Hong by capping the air gaps with the conductive layer as taught by Dubin to have the structure, wherein the metal cap physically contacts the second dielectric layer, in order to reduce the incidence of diffusion and electromigration to provide improved air-gap interconnection structure (Dubin, Col. Lines 13-15; Col. 2, lines 53-67; Col. 3, lines 119; Col. 4, line 50-67; Col. 5, lines 1-60).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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