Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 07/30/24. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 07/30/24 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. §102(a)(1) and (a)(2) as being unpatentable over Lee (US 20170141188 A1).
Regarding claim 1, Lee discloses a semiconductor device structure, comprising:
a plurality of semiconductor nanostructures over a substrate (see 120);
two epitaxial structures over the substrate, wherein each of the semiconductor nanostructures is between the epitaxial structures (110 between 120);
a gate stack wrapped around the semiconductor nanostructures (see fig 2a, 280 around 110),
wherein the gate stack (see fig 2a) has a gate dielectric layer 270 and a gate electrode280; and
a dielectric stressor structure between the gate stack and the substrate (see 110A),
wherein the gate dielectric layer extends along and beyond first opposite sidewalls of the dielectric stressor structure (see 290 extending beyond 110a).
Regarding claim 2, Lee discloses the semiconductor device structure as claimed in claim 1, wherein the epitaxial structures extend upward along second opposite sidewalls of the dielectric stressor structure, surpassing a top surface of the dielectric stressor structure (see fig 3 and 1 disclosing 200 exceeds the boundaries of 110a).
Regarding claim 3, Lee discloses the semiconductor device structure as claimed in claim 1, wherein the dielectric stressor structure is made of SiN, SiCN, SiOCN, SiOC, or a combination thereof (see para [0098] disclosing).
Regarding claim 4, Lee discloses the semiconductor device structure as claimed in claim 1, wherein the epitaxial structures are in direct contact with the dielectric stressor structure (see fig 3 disclosing 110a in contact with 120).
Regarding claim 5, Lee discloses the semiconductor device structure as claimed in claim 1, further comprising a plurality of inner spacers, wherein each of the inner spacers is between the gate stack and one of the epitaxial structures (see fig 3 disclosing inner spacers 110b).
Regarding claim 6, Lee discloses the semiconductor device structure as claimed in claim 5, wherein the inner spacers and the dielectric stressor structure are made of different materials (see 110b and 110a are separated materials).
Regarding claim 7, Lee discloses the semiconductor device structure as claimed in claim 5, further comprising a dielectric element between the inner spacers and the dielectric stressor structure (see 290).
Regarding claim 8, Lee discloses the semiconductor device structure as claimed in claim 7, wherein the semiconductor nanostructures are made of a semiconductor material (see para [0070]), and the dielectric element is made of an oxide material of the semiconductor material (see 270/290, para [0062]).
Regarding claim 9, Lee discloses the semiconductor device structure as claimed in claim 1, wherein a bottommost surface of the epitaxial structure is closer to the substrate than a topmost surface of the dielectric stressor structure (see 200/210 is recessed into 150 in fig 1l).
Regarding claim 10, lee discloses the semiconductor device structure as claimed in claim 1, wherein the dielectric stressor structure extends exceeding opposite edges of the gate stack (see fig3 110b).
Regarding claim 11, Lee discloses the semiconductor device structure as claimed in claim 1, wherein a topmost surface of the dielectric stressor structure is between the substrate and a bottommost surface of the semiconductor nanostructures (see fig 3, top of 110a/b between 120 and 100).
Regarding claim 12, Lee discloses a semiconductor device structure, comprising:
a plurality of channel structures over a substrate (see fig 1l, 120 over 100);
a gate stack wrapped around each of the channel structures;
an epitaxial structure abutting the channel structures (see 260 surrounding 120); and
a dielectric stressor structure between the substrate and a bottom of the channel structures (see 110a between 120’s fig 3),
wherein the gate stack extends upwards along a sidewall of the dielectric stressor structure, reaching beyond both a bottom and a top of the dielectric stressor structure (see 260 extending upwards to surround the stack structures, including the stressors).
Regarding claim 13, Lee discloses the semiconductor device structure as claimed in claim 12, wherein a top surface of the dielectric stressor structure is vertically between a top surface of the epitaxial structures and a bottom surface of the epitaxial structures (see figs 1 and 3 disclosing 110 between tops and bottoms of 200).
Regarding claim 14, Lee discloses the semiconductor device structure as claimed in claim 12, wherein the dielectric stressor structure is in direct contact with the epitaxial structure (see figs 1l and 3 disclosing 110 is in contact with 200).
Regarding claim 15, Lee discloses the semiconductor device structure as claimed in claim 12, further comprising: a second epitaxial structure abutting the channel structures, wherein the channel structures are sandwiched between the epitaxial structure and the second epitaxial structure, and the dielectric stressor structure is sandwiched between the epitaxial structure and the second epitaxial structure (see 210 abutting 200).
Regarding claim 16, Lee discloses a semiconductor device structure, comprising:
a plurality of semiconductor nanostructures (see fig 1l, disclosing 110/120);
a first epitaxial structure and a second epitaxial structure (see left and right 200),
wherein each of the semiconductor nanostructures is sandwiched between the first epitaxial structure and the second epitaxial structure (see 120/110 between 200);
a gate stack wrapped around the semiconductor nanostructures (see 260 wrapping the channels); and
a dielectric stressor structure below the semiconductor nanostructures (see fig 3, 110a), wherein the dielectric stressor structure is sandwiched between the epitaxial structure and the second epitaxial structure (see fig 3 110 is between 210 and 200).
Regarding claim 17, Lee discloses the semiconductor device structure as claimed in claim 16, wherein the first epitaxial structure and the second epitaxial structure extend upward along sidewalls of the dielectric stressor structure, surpassing a top surface of the dielectric stressor structure (see figs 1 and 3 disclosing 200 and 210 extending upwards from substrate).
Regarding claim 18, Lee discloses the semiconductor device structure as claimed in claim 16, further comprising a seam surrounded by the dielectric stressor structure (see 110, disclosing multiple seams, i.e. 110a/b).
Regarding claim 19, Lee discloses the semiconductor device structure as claimed in claim 16, wherein the first epitaxial structure and the second epitaxial structure are in direct contact with the dielectric stressor structure (see 200/210 formed in contact with 220).
Regarding claim 20, Lee discloses the semiconductor device structure as claimed in claim 16, wherein the dielectric stressor structure is thicker than each of the semiconductor nanostructures (see 110 with 110a/b is thicker than 120).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brit Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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