DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art.
The Examiner would like to specifically point out that the term “bottom-up manner”, as used in claim 6, is interpreted to mean that a deposition rate is higher on a bottom surface of an opening than on other surfaces of the opening, as described in paragraph [0061] of the Specification.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD FOR FORMING A MULTI-LAYER ETCH MASK FOR FORMING A SEMICONDUCTOR DEVICE
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 7, 9-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai; Wan-Lin et al. (US 2019/0006227; hereinafter Tsai) in view of in view of Briggs; Benjamin D. et al. (US 2019/0067087; hereinafter Briggs).
Regarding claim 1, Tsai discloses method (900; Fig 9; entire document), comprising:
forming a patterned amorphous silicon layer (110, can be amorphous silicon; Fig 1; ¶ [0018, 0043]) over a substrate (120; Fig 1; ¶ [0018, 0043]);
depositing a first spacer layer (115; Fig 1; ¶ [0018, 0043]) over the patterned amorphous silicon layer;
forming a photoresist (200; Figs 2,6; ¶ [0020, 0044]) having an opening (210; Figs 2,6; ¶ [0025, 0045]) exposing a portion of the first spacer layer;
depositing a second spacer layer (610; Fig 6; ¶ [0033, 0050]) in the opening of the photoresist and over the first spacer layer;
forming a hard mask layer (620; Fig 6; ¶ [0033, 0050]) in the opening of the photoresist and over second spacer layer; and,
after forming the hard mask layer in the opening of the photoresist, removing the photoresist (Fig 7; ¶ [0040]).
Tsai does not disclose forming a dielectric layer over a substrate; forming the patterned amorphous silicon layer over the dielectric layer; and, etching the dielectric layer by using the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask.
In the same field of endeavor, Briggs discloses a method of forming a semiconductor device (100; Fig 2; ¶ [0029]), comprising forming a dielectric layer (108; Fig 2; ¶ [0035]) over a substrate (102; Fig 2; ¶ [0029]). Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined the method of Tsai with the method of Briggs by forming a dielectric layer on a substrate as taught by Briggs (that is, by substituting the substrate and dielectric layer of Briggs for the substrate of Tsai), and forming the patterned amorphous silicon layer over the dielectric layer, and etching the dielectric layer by using the first spacer layer (Tsai; 115; Fig 8), the second spacer layer (Tsai; 610; Fig 8), and the hard mask layer (Tsai; 620; Fig 8) as an etch mask. One would have been motivated to do this in order to successfully pattern a structure benefiting from the high aspect ratio dielectric layer gap fill provided by the disclosures of Tsai (Tsai; Abst). One would have had a reasonable expectation of success because the method of Tsai is a patterning method transferable to any number of semiconductor device applications (Tsai; ¶ [0065]) and because Tsai discloses that the substrate 120 can be a partially fabricated wafer (¶ [0018]).
Regarding claim 2, Tsai in view of Briggs discloses the method of claim 1, further comprising etching horizontal portions of the first spacer layer (Tsai; 115; Figs 7-8; ¶ [0041]; horizontal portions shown in Fig 7 have been removed in Fig 9) that are exposed by the hard mask layer (Tsai; 620; Fig 7) after removing the photoresist (Tsai; 200; Fig 7 is shown after removal of 200; ¶ [0040]) and prior to etching the dielectric layer (as applied to claim 1, with reference to Figs 7-8 of Tsai, the dielectric layer is still present in Fig 8 (the dielectric/substrate of Briggs substituting for 120 of Tsai; the entire mask structure of Tsai being on the dielectric to be used as an etching mask).
Regarding claim 5, Tsai in view of Briggs discloses the method of claim 1, wherein a portion of the first spacer layer (Tsai; 115) is free of coverage by the second spacer layer (Tsai; 610; as shown in Fig 8, portions of 115 along sidewalls of 110 are free of coverage by 610).
Regarding claim 7, Tsai in view of Briggs discloses the method of claim 1, further comprising etching back the hard mask layer (Tsai; 620) prior to removing the photoresist (Tsai; 200; ¶ [0040]; 610 is over 200, such that during the described etch-back process 610 is removed prior to 200; further, as also described, any remaining photoresist (after the etch-back process) can be stripped {¶ [0057}).
Regarding claim 9, Tsai discloses method (900; Fig 9; entire document), comprising:
forming a patterned amorphous silicon layer (110, can be amorphous silicon; Fig 1; ¶ [0018, 0043]) over a substrate (120; Fig 1; ¶ [0018, 0043]);
depositing a first spacer layer (115; Fig 1; ¶ [0018, 0043]) over the patterned amorphous silicon layer;
forming a second spacer layer (610; Fig 8; ¶ [0033-40]) covering a first portion of the first spacer layer, while a second portion of the first spacer layer is free of coverage by the second spacer layer (as shown in Fig 8, and associated description, 610 covers only a portion of 115);
forming a hard mask layer (620; Figs 6-8; ¶ [0033, 0050]) over the second spacer layer;
Tsai does not disclose forming a dielectric layer over a substrate; forming the patterned amorphous silicon layer over the dielectric layer; and, etching the dielectric layer by using the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask.
In the same field of endeavor, Briggs discloses a method of forming a semiconductor device (100; Fig 2; ¶ [0029]), comprising forming a dielectric layer (108; Fig 2; ¶ [0035]) over a substrate (102; Fig 2; ¶ [0029]). Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined the method of Tsai with the method of Briggs by forming a dielectric layer on a substrate as taught by Briggs (that is, by substituting the substrate and dielectric layer of Briggs for the substrate of Tsai), and forming the patterned amorphous silicon layer over the dielectric layer, and etching the dielectric layer by using the first spacer layer (Tsai; 115; Fig 8), the second spacer layer (Tsai; 610; Fig 8), and the hard mask layer (Tsai; 620; Fig 8) as an etch mask. One would have been motivated to do this in order to successfully pattern a structure benefiting from the high aspect ratio dielectric layer gap fill provided by the disclosures of Tsai (Tsai; Abst). One would have had a reasonable expectation of success because the method of Tsai is a patterning method transferable to any number of semiconductor device applications (Tsai; ¶ [0065]) and because Tsai discloses that the substrate 120 can be a partially fabricated wafer (¶ [0018]).
Regarding claim 10, Tsai in view of Briggs discloses the method of claim 9, wherein forming the second spacer layer (Tsai; 610) comprises:
forming a photoresist (Tsai; 200; Figs 2,6; ¶ [0020-25, 0044]) covering the second portion of the first spacer layer and having an opening (Tsai; 210; Figs 2,6; ¶ [0025, 0045]) exposing the first portion of the first spacer layer; and
depositing the second spacer layer (Tsai; 610; Fig 6; ¶ [0033, 0050]) in the opening of the photoresist.
Regarding claim 11, Tsai in view of Briggs discloses the method of claim 10, wherein the hard mask layer (Tsai; 620; Fig 6; ¶ [0033, 0050]) is formed in the opening of the photoresist, and the method further comprises etching back the hard mask layer (Tsai; 200; Fig. 7; ¶ [0040]).
Regarding claim 13, Tsai in view of Briggs discloses the method of claim 9, wherein the hard mask layer (Tsai; 620; Fig 6) is spaced apart from the first spacer layer (Tsai; 115; Fig 6) through the second spacer layer (Tsai; 610; Fig 6; as shown in Fig 6).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai; Wan-Lin et al. (US 2019/0006227; hereinafter Tsai) in view of in view of Briggs; Benjamin D. et al. (US 2019/0067087; hereinafter Briggs) and further in view of Back; Doosan et al. (US 2022/0190132; hereinafter back).
Regarding claim 4, Tsai in view of Briggs discloses the method of claim 1, wherein the second spacer layer (Tsai; 610; Fig 6) is deposited using a plasma-enhanced ALD process (PEALD; Tsai; ¶ [0035]),
but does not disclose wherein the first spacer layer (Tsai; 115; Figs 1,6) is deposited using a plasma-free atomic layer deposition (ALD).
In the same field of endeavor, Back discloses a semiconductor device including first and second spacer layers wherein a first spacer layer (310p; Fig 5A; ¶ [0052]) is deposited using a plasma-free atomic layer deposition (ALD), and a second spacer layer (320p; Fig 5E; ¶ [0057]) is deposited using a plasma-enhanced ALD process. Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the teaching of Back with the method of Tsai in view of Briggs to satisfy the limitation of claim 3. One would have been motivated to do this in order to control a content ratio of constituents of the second spacer layer to realize a different refractive index, or other film property, as compared to the first spacer layer (Back; ¶ [0057]; Abst). One would have had a reasonable expectation of success because each deposition method is well-known in the art, and because Back has disclosed their use for the same
Allowable Subject Matter
Claims 15-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a patterned amorphous silicon layer over the dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; forming a second spacer layer covering a first portion of the first spacer layer, while a second portion of the first spacer layer is free of coverage by the second spacer layer; forming a hard mask layer over the second spacer layer; performing an etching process on the first spacer layer, the second spacer layer, and the hard mask layer to expose the patterned amorphous silicon layer; removing a portion of the patterned amorphous silicon layer; and etching the dielectric layer by using the first spacer layer, the second spacer layer, the hard mask layer, and a remaining portion of the patterned amorphous silicon layer as an etch mask”, along with the additional limitations of Claim 1.
The prior art Tsai, cited above, does not disclose performing an etching process on the first spacer layer, the second spacer layer, and the hard mask layer to expose the patterned amorphous silicon layer; removing a portion of the patterned amorphous silicon layer; and etching the dielectric layer by using the first spacer layer, the second spacer layer, the hard mask layer, and a remaining portion of the patterned amorphous silicon layer as an etch mask.
The prior art Liu; Chi-Chun et al. (US 2021/0151377; hereinafter Liu) discloses a method, comprising: forming a dielectric layer (110; Fig 3) over a substrate; forming a patterned amorphous silicon layer (140; Fig 3) over the dielectric layer; depositing a first spacer layer (150; Fig 3) over the patterned amorphous silicon layer; forming a second spacer layer (180; Fig 3; which become spacer plugs 190; Fig 10) covering a first portion of the first spacer layer (portion within opening 165), while a second portion of the first spacer layer is free of coverage by the second spacer layer (portion covered by 160, outside 165); forming a hard mask layer (200; Fig 10) over the second spacer layer (190; Fig 10).
Liu discloses performing an etching to remove a portion of the patterned amorphous silicon layer (140; Fig 17) through an opening in an organic planarization layer (160; Fig 17) and an anti-reflection coating (220; Fig 17), and etching a second hardmask layer (130; Fig 22) by using the second spacer layer (spacer plugs 190; Fig 22) and a remaining portion of the patterned amorphous silicon layer (140; Fig 22) as an etch mask (first spacer 150 and hardmask layer 200 having been removed).
Liu does not disclose nor render obvious performing an etching process on the first spacer layer, the second spacer layer, and the hard mask layer to expose the patterned amorphous silicon layer, removing a portion of the patterned amorphous silicon layer, and etching the dielectric layer by using the first spacer layer, the second spacer layer, the hard mask layer, and a remaining portion of the patterned amorphous silicon layer as an etch mask.
Claims 3, 6, 8, 12 and 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the hard mask layer is in contact with a sidewall of the photoresist”, along with the additional limitations of Claim 1.
Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the second spacer layer is deposited in the opening via a bottom-up manner”, along with the additional limitations of Claim 1.
Regarding claim 8, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the second spacer layer has a higher deposition rate on the first spacer layer than on the photoresist”, along with the additional limitations of Claim 1.
Regarding claim 12, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein etching back the hard mask layer is performed such that a topmost surface of the hard mask layer is lower than a topmost surface of the second spacer layer”, along with the additional limitations of Claim 1.
Regarding claim 14, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein a topmost surface of the second spacer layer is free of coverage by the hard mask layer”, along with the additional limitations of Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lazzarino; Frederic et al. (US 2020/0168500; the prior art discloses a method of forming an interconnect structure including spacer and mandrel lines of different materials and forming a cut mask for patterning the lines into segments).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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