DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 is objected to because of the following informalities:
On lines 9-10, “a second bottom isolation feature directly under the second bottom isolation feature” should be amended with “a second bottom isolation feature directly under the second bottom semiconductor layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 14 and 17 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Xie et al. (US 10,998,234; hereinafter Xie).
Regarding claim 1, Xie discloses for A semiconductor structure, comprising:
a substrate (substrate 204, Fig. 11A-B);
a bottom isolation feature (bottom isolation structure 202 including bottom isolation layer 506/middle isolation layer 1002/top isolation layer 504, Fig. 11A-B) formed over the substrate (204, Fig. 11A-B);
a bottom semiconductor layer (semiconductor buffer layer 702, Fig. 11A-B) formed over the bottom isolation feature (202, Fig. 11A-B);
nanostructures (semiconductor layer 214, Fig. 11A-B) formed over the bottom semiconductor layer (702, Fig. 11A-B); and
a source/drain structure (source/drain regions 704, Fig. 11A-B) attached to the nanostructures (214, Fig. 11A-B) and covering a portion of the bottom isolation feature (a portion of 506, Fig. 11A-B), because the source/drain region 704 by Xie vertically covers or overlaps a portion of the bottom isolation structure 202 (Fig. 11A-B).
Regarding claim 2, Xie further discloses for The semiconductor structure as claimed in claim 1 that a gate structure (gate 1102, Fig. 11A-B) wrapping around the nanostructures (214, Fig. 11A-B), wherein the gate structure (1102, Fig. 11A-B) covers a top surface of the bottom semiconductor layer (top surface of top isolation layer 504, Fig. 11A-B), because the gate 1102 by Xie vertically covers or overlaps the top surface of the top isolation layer 504 (Fig. 11A-B).
Regarding claim 3, Xie further discloses for The semiconductor structure as claimed in claim 1 that inner spacers (inner spacers 602, Fig. 11A-B) formed between the nanostructures (214, Fig. 11A-B), wherein the inner spacers (602, Fig. 11A-B) partially cover the bottom semiconductor layer (506, Fig. 11A-B).
Regarding claim 4, Xie further discloses for The semiconductor structure as claimed in claim 3 that the bottom isolation feature (202, Fig. 11A-B) covers a sidewall of the bottom semiconductor layer (sidewall of 702, Fig. 11A-B), because the top isolation layer 504 of the bottom isolation structure 202 covers sidewalls of the semiconductor buffer layer 702 (Fig. 11A-B).
Regarding claim 5, Xie further discloses for The semiconductor structure as claimed in claim 4 that the bottom isolation feature (202, Fig. 11A-B) is in contact with the inner spacers (602, Fig. 11A-B).
Regarding claim 7, Xie further discloses for The semiconductor structure as claimed in claim 1 that a bottommost portion of the bottom isolation feature (bottom isolation layer 506 of 202, Fig. 11A-B) is lower than a bottommost surface of the nanostructures (bottommost surface of 214, Fig. 11A-B).
Regarding claim 8, Xie further discloses for The semiconductor structure as claimed in claim 1 that a width of the bottom semiconductor layer (width of 702, Fig. 11A-B) is smaller than a width of one of the nanostructures (width of 214, Fig. 11A-B).
Regarding claim 9, Xie discloses for A semiconductor structure, comprising:
a first base fin structure (fin region of 204 between shallow trench isolation 218, Fig. 11B) protruding from a substrate (substrate 204, Fig. 11B);
a first bottom isolation feature (bottom isolation structure 202, Fig. 11A-B) formed over the first base fin structure (fin region of 204, Fig. 11B);
a first bottom semiconductor layer (bottom semiconductor layer 214, Fig. 11A-B) formed over a first region of the first bottom isolation feature (vertically overlapped region of 202 with 214, Fig. 11A-B), because Applicants do not specifically claim how a bottom semiconductor layer and nanostructures are structurally different each other and/or what the bottom semiconductor layer and nanostructures are made of, the semiconductor layer 214 at the bottom of the stack in Xie can correspond to the claimed bottom semiconductor layer;
first nanostructures (middle and top semiconductor layers 214, Fig. 11A-B) formed over the first bottom semiconductor layer (bottom 214, Fig. 11A-B);
a first gate structure (1102, Fig. 11A-B) wrapping around the first nanostructures (middle and top 214, Fig. 11A-B); and
a first source/drain structure (source/drain region 704, Fig. 11A-B) attached to the first nanostructures (middle and top 214, Fig. 11A-B) and over a second region of the first bottom isolation feature (vertically overlapped region of 202 with 704, Fig. 11A-B),
wherein a bottom portion of the second region of the first bottom isolation feature (bottom portion of a region of 202 directly below 704, Fig. 11A) is lower than a bottom portion of the first region of first bottom isolation feature (bottom portion of a region of 202 directly below 214, Fig. 11A), because the bottom portion of the bottom isolation structure 202 directly below the source/drain region 704 is recessed due to the semiconductor buffer layer 702, and therefore, it is lower than the bottom portion of 202 directly below the semiconductor layer 214 (Fig. 11A).
Regarding claim 14, Xie discloses for A semiconductor structure, comprising:
a first transistor (center transistor of the semiconductor structure 100, Fig. 11A), comprising first nanostructures (center stack of semiconductor layers 214, Fig. 11A) spaced apart from each other in a first direction (vertical direction, Fig. 11A);
a first source/drain structure (left source/drain region 704, Fig. 11A) and a second source/drain structure (right source/drain region 704, Fig. 11A) attached to opposite sides of the first nanostructure (center stack of 214, Fig. 11A) in a second direction (lateral direction, Fig. 11A);
a first gate structure (gate 1102, Fig. 11A-B) wrapping around the first nanostructures (center stack of 214, Fig. 11A-B);
a first bottom semiconductor layer (bottom semiconductor layer 214 at the center of Fig. 11A) directly under the first gate structure (1102, Fig. 11A), because Applicants do not specifically claim how a first bottom semiconductor layer and first nanostructures are structurally different each other and/or what the first bottom semiconductor layer and first nanostructures are made of, the semiconductor layer 214 at the bottom of the stack at the center of Fig. 11A in Xie can correspond to the claimed first bottom semiconductor layer and formed directly under the gate 1102 (Fig. 11A-B); and
a first bottom isolation feature (bottom isolation structure 202 at the center of Fig. 11A) continuously extending under the first source/drain structure (under left 704, Fig. 11A), the first bottom isolation feature (under bottom 214, Fig. 11A-B), and the second source/drain structure (under right 704, Fig. 11A).
Regarding claim 17, Xie further discloses for The semiconductor structure as claimed in claim 14 that first inner spacers (center inner spacers 602, Fig. 11A) under the first nanostructures (center stack of 214, Fig. 11A), wherein the first bottom semiconductor layer (center bottom 214, Fig. 11A) is sandwiched between a bottommost one of the first inner spacers (center bottommost 602, Fig. 11A) and the first bottom isolation feature (202, Fig. 11A) in the first direction (vertical direction, Fig. 11A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 are rejected under 35 U.S.C. 103 as being unpatentable over by Xie et al. (US 10,998,234; hereinafter Xie).
Regarding claim 18, Xie discloses that a second transistor (right transistor of the semiconductor structure 100, Fig. 11A), comprising second nanostructures (right stack of 214, Fig. 11A) spaced apart from each other in the first direction (vertical direction, Fig. 11A);
a second gate structure (gate 1102, Fig. 11A-B) wrapping around the second nanostructures (right stack of 214, Fig. 11A);
a second bottom semiconductor layer (right bottom semiconductor layer 214, Fig. 11A) directly under the second gate structure (directly under 1102, Fig. 11A), because Applicants do not specifically claim how a second bottom semiconductor layer and second nanostructures are structurally different each other and/or what the second bottom semiconductor layer and second nanostructures are made of, the semiconductor layer 214 at the bottom of the stack at the right side of Fig. 11A in Xie can correspond to the claimed second bottom semiconductor layer and formed directly under the gate 1102 (Fig. 11A-B); and
a second bottom isolation feature (bottom isolation structure 202 at the right side of Fig. 11A) directly under the second bottom isolation feature (see Claim Objections above).
Xie does not explicitly disclose that a third source/drain structure and a fourth source/drain structure attached to opposite sides of the second nanostructure in the second direction; the second bottom isolation feature attaching to the third source/drain structure and the fourth source/drain structure in the second direction.
However, one of ordinary skill in the art would have understood that Xie’s illustrated gate-all-around FET structure represents a transistor cell unit suitable for inclusion in a larger transistor array. In such an array, the source/drain regions extend laterally adjacent to the nanostructure stack and gate structure, thereby providing source/drain structures on opposite sides of adjacent nanostructures and the corresponding bottom isolation feature. This arrangement represents the predictable use of conventional transistor array layouts for gate-all-around FETs.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to manufacture an array of gate-all-around FETs in which nanostructure is coupled to laterally adjacent source/drain regions.
Allowable Subject Matter
Claims 6, 10-13, 15-16, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art cited in this office action does not teach the claimed limitations, “a void is formed between the source/drain structure and the bottom isolation feature” of claim 6, “a void is formed under the first source/drain structure” of claim 10, “a seam is formed…” of claim 11, “a bottommost surface of the second bottom isolation feature is higher than a bottommost surface of the first bottom isolation feature” of claim 12, “the first portion and the second portion of the first bottom isolation feature have rounded bottom surfaces” of claim 15, and “a bottommost portion of the first bottom isolation feature is lower than a bottommost portion of the second bottom isolation feature” of claim 19. Claim 13 depends on claim 12 and claim 20 depends on claim 19.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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