DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,398,271. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application claims similar features as the issued patent. In other words, the current invention is broader than the issued patent. The current application recites similar limitations as the issued patent such as a memory array comprising one or more rows of memory cells and one or more columns of memory cells, a comparator circuitry operably connected to a respective column of memory cells in the one or more columns of memory cells, wherein the comparator circuit is configured to: generate a first precompute signal and a second precompute, wherein the comparator circuit being configured to generate the first precompute signal and the second precompute signal comprises the comparator circuit being configured to generate the first precompute signal and the second precompute signal from a previous memory output signal and a Compare input and Control (CIC) signal before a cell data signal; receive the cell data signal from a memory cell in a respective column of memory cells; and select, based on the cell data signal, one of the first precompute signal and the second precompute signal to output from the comparator circuitry as a memory output signal for the memory array.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,136,454 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application claims similar features as the issued patent. In other words, the current invention is broader than the issued patent. The current application recites similar limitations as the issued patent such as a memory array comprising one or more rows of memory cells and one or more columns of memory cells, a comparator circuitry operably connected to a respective column of memory cells in the one or more columns of memory cells, wherein the comparator circuit is configured to: generate a first precompute signal and a second precompute, wherein the comparator circuit being configured to generate the first precompute signal and the second precompute signal comprises the comparator circuit being configured to generate the first precompute signal and the second precompute signal from a previous memory output signal and a Compare input and Control (CIC) signal before a cell data signal; receive the cell data signal from a memory cell in a respective column of memory cells; and select, based on the cell data signal, one of the first precompute signal and the second precompute signal to output from the comparator circuitry as a memory output signal for the memory array.
Allowable Subject Matter
Currently, the claims are rejected under double patenting rejections. The claims will be allowed if the double patenting rejections above are overcame.
The following is an examiner’s statement of reasons for allowance:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claim 1, generate a first precompute signal and a second precompute, wherein the comparator circuit being configured to generate the first precompute signal and the second precompute signal comprises the comparator circuit being configured to generate the first precompute signal and the second precompute signal from a previous memory output signal and a Compare input and Control (CIC) signal before a cell data signal; receive the cell data signal from a memory cell in a respective column of memory cells; and select, based on the cell data signal, one of the first precompute signal and the second precompute signal to output from the comparator circuitry as a memory output signal for the memory array.
With regards to claim 10, selecting, based on the cell data signal, one of a first precompute signal or a second precompute signal as a first signal read from the first memory cell; determining that a second memory cell is to be read; receiving, in response to determining that the second memory cell is to be read, a second cell data signal from the second memory cell; and selecting, based the second cell data signal, one of the first precompute signal and the second precompute signal as a second signal read from the second memory cell.
With regards to claim 15, generate a first precompute signal and a second precompute signal, wherein the precompute circuit being configured to generate the first precompute signal and the second precompute signal comprises the precompute circuit being configured to produce the first precompute signal and the second precompute signal from a previous memory output signal and a compare input and control (CIC) signal before a cell data signal; and a select circuit operably connected to the precompute circuit, wherein the select circuit is configured to: receive an inverted cell data signal from a memory cell of the memory device; and select, based on the inverted cell data signal, one of the first precompute signal and the second precompute signal to output as a memory output signal for the memory cell.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824