Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 10-13, 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw et al.(US 20140210043 A1, hereafter Wang).
Regarding Claim 1, Wang discloses:
A method of operating a semiconductor device(See Figs. 1-8) comprising:
Receiving, through a first conductive structure(Fig. 1 [133]) electrically connected to a gate(Fig. 1 [110]) of a metal-oxide-semiconductor(MOS) device, a word line voltage(Fig. 1 [Word Line], See paragraph 0073);
Receiving, through a second conductive structure(Fig. 1 [132]), a bit line voltage(See paragraph 0058) greater than a predetermined voltage(“sufficiently high”); and
Creating a first channel(See paragraph 0058, a channel through Fig. 1 [136]) between the second conductive structure(Fig. 1 [134]) and a third conductive structure(Fig. 1 [114]) electrically coupled to one of a source or drain(Fig. 1 [108]) of the MOS device(Fig. 1 [106/108/110/116]).
Regarding Claim 2, Wang further discloses:
Receiving the bit line voltage(See above) through a first via structure(Fig. 1 [132]) disposed directly above the second conductive structure(Fig. 1 [134]).
Regarding Claim 3, Wang further discloses:
The first channel(See Fig. 1 [136]) is configured to be formed in a dielectric material to electrically short the second conductive structure(Fig. 1 [134]) and the third conductive structure(Fig. 1 [114]).
Regarding Claim 4, Wang further discloses:
The dielectric material(Fig. 1 [136]) is disposed over at least the third conductive structure(Fig. 1 [114]).
Regarding Claim 5, Wang further discloses:
The second(Fig. 1 [134]) and third conductive structures(Fig. 1 [114]) extend in a first direction(horizontally) and are spaced from each other in a second direction(downwards) perpendicular to the first direction.
Regarding Claim 6, Wang further discloses:
The first conductive structure(Fig. 1 [133]) extends in the second direction(downwards).
Regarding Claim 10, Wang discloses:
A method of operating a semiconductor device(Figs. 1-8) comprising:
Receiving, through a first conductive structure(Fig. 1 [133]) electrically connected to a gate(Fig. 1 [110]) of a metal-oxide-semiconductor(MOS) device, a word line voltage(Fig. 1 [Word Line], See paragraph 0073);
Receiving, through a second conductive structure(Fig. 1 [132]), a bit line voltage(See paragraph 0058) greater than a predetermined voltage(“sufficiently high”); and
Creating a first channel(See paragraph 0058, a channel through Fig. 1 [136]) between the second conductive structure(Fig. 1 [134]) and a third conductive structure(Fig. 1 [114]) electrically coupled to one of a source or drain(Fig. 1 [108]) of the MOS device(Fig. 1 [106/108/110/116]),
wherein the second(Fig. 1 [134]) and third conductive structures(Fig. 1 [114]) extend in a first direction(horizontally) and are spaced from each other in a second direction(downwards) perpendicular to the first direction.
Regarding Claim 11, Wang further discloses:
Receiving the bit line voltage(See above) through a first via structure(Fig. 1 [132]) disposed directly above the second conductive structure(Fig. 1 [134]).
Regarding Claim 12, Wang further discloses:
The first channel(See Fig. 1 [136]) is configured to be formed in a dielectric material to electrically short the second conductive structure(Fig. 1 [134]) and the third conductive structure(Fig. 1 [114]).
Regarding Claim 13, Wang further discloses:
The dielectric material(Fig. 1 [136]) is disposed over at least the third conductive structure(Fig. 1 [114]).
Regarding Claim 17, Wang discloses:
A method of operating a semiconductor device(See Figs. 1-8) comprising:
Receiving, through a first conductive structure(Fig. 1 [133]) electrically connected to a gate(Fig. 1 [110]) of a metal-oxide-semiconductor(MOS) device, a word line voltage(Fig. 1 [Word Line], See paragraph 0073);
Receiving, through a second conductive structure(Fig. 1 [128]) extending in a first direction(sideways), a bit line voltage(See paragraph 0058); and
Creating a channel between a third conductive structure(Fig. 1 [132]) and a fourth conductive structure(Fig. 1 [114]) each extending in a second direction(vertically), wherein the fourth conductive structure(Fig. 1 [114]) is coupled to one of a drain or a source(Fig. 1 [108]) of the MOS device(Fig. 1 [106/108/110/116]);
Wherein the second conductive structure(Fig. 1 [128]) is disposed above the third and fourth conductive structures(Fig. 1 [132/114]).
Regarding Claim 18, Wang further discloses:
Receiving the bit line voltage through a via structure(Fig. 1 [130]) coupling the second conductive structure(Fig. 1 [128]) and to the third conductive structure(Fig. 1 [132]);
Wherein the via structure(Fig. 1 [130]) is disposed directly above the third conductive structure(Fig. 1 [132])/
Regarding Claim 19, Wang further discloses:
The via structure(Fig. 1 [130]) is spaced from the fourth conductive structure(Fig. 1 [114]) in the second direction.
Regarding Claim 20, Wang further discloses:
The channel(See Fig. 1 [136]) is configured to be formed in a dielectric material(Fig. 1 [136]) to electrically short the third conductive structure(Fig. 1 [132]) and the fourth conductive structure(Fig. 1 [114]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-9, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding Claim 7,
In the embodiment of Claim 1, Wang does not teach or disclose receiving through a fourth conductive structure the bit line voltage and creating a second channel between the fourth conductive structure and the third conductive structure.
In an alternative embodiment, Wang shows a fourth conductive structure(Fig. 28 [2602]) receiving a bit line voltage(See paragraph 0119) and creating a second channel between the fourth conductive structure(Fig. 28 [2602]) and the third conductive structure(Fig. 28 [2106]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to implement features from Wang’s alternate embodiment to achieve a method in accordance with the claims at hand. One might have been motivated to provide this alternate antifuse structure to increase the amount of surface area of the antifuse plates and improve the reliability of the programming operation. Performing this modification would have generated a predictable result by generating an alternate embodiment of a method of operating Wang’s device.
Regarding Claim 8,
In the embodiment of Claim 1, Wang does not teach or disclose receiving the bit line voltage through a second via structure disposed directly above the fourth conductive structure.
In an alternative embodiment, Wang shows a fourth conductive structure(Fig. 28 [2802]) receiving a bit line voltage(See paragraph 0119) and receiving this signal through a second via(Fig. 28 [2804]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to implement features from Wang’s alternate embodiment to achieve a method in accordance with the claims at hand. One might have been motivated to provide this alternate antifuse structure to increase the amount of surface area of the antifuse plates and improve the reliability of the programming operation. Performing this modification would have generated a predictable result by generating an alternate embodiment of a method of operating Wang’s device.
Regarding Claim 9, Wang further discloses:
The second, third, and fourth(Fig. 1 [132/114/128]) conductive structures extend in a first direction(sideways) and are spaced from each other in a second direction perpendicular to the first direction.
Regarding Claim 14,
In the embodiment of Claim 1, Wang does not teach or disclose receiving through a fourth conductive structure the bit line voltage and creating a second channel between the fourth conductive structure and the third conductive structure.
In an alternative embodiment, Wang shows a fourth conductive structure(Fig. 28 [2602]) receiving a bit line voltage(See paragraph 0119) and creating a second channel between the fourth conductive structure(Fig. 28 [2602]) and the third conductive structure(Fig. 28 [2106]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to implement features from Wang’s alternate embodiment to achieve a method in accordance with the claims at hand. One might have been motivated to provide this alternate antifuse structure to increase the amount of surface area of the antifuse plates and improve the reliability of the programming operation. Performing this modification would have generated a predictable result by generating an alternate embodiment of a method of operating Wang’s device.
Regarding Claim 15,
In the embodiment of Claim 1, Wang does not teach or disclose receiving the bit line voltage through a second via structure disposed directly above the fourth conductive structure.
In an alternative embodiment, Wang shows a fourth conductive structure(Fig. 28 [2802]) receiving a bit line voltage(See paragraph 0119) and receiving this signal through a second via(Fig. 28 [2804]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to implement features from Wang’s alternate embodiment to achieve a method in accordance with the claims at hand. One might have been motivated to provide this alternate antifuse structure to increase the amount of surface area of the antifuse plates and improve the reliability of the programming operation. Performing this modification would have generated a predictable result by generating an alternate embodiment of a method of operating Wang’s device.
Regarding Claim 16, Wang further discloses:
The second, third, and fourth(Fig. 1 [132/114/128]) conductive structures extend in a first direction(sideways) and are spaced from each other in a second direction perpendicular to the first direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Okada et al.(US 20210257376 A1) discloses an antifuse cell. Chung et al.(US 10770160 B2) discloses an antifuse cell. Chang et al.(US 20200058660 A1) discloses an antifuse cell.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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