DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Fig. 27K, Claims 1-20) in the reply filed on 07/02/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the semiconductor structure passes through a top and a bottom of at least one of the nanostructures” the metes and bounds of this limitation cannot be determined. Two mutually exclusive construction are available. Where the semiconductor structure physically traverses the body of a nanostructure, entering its top surface and exiting at its bottom surface or
the semiconductor structure merely spans, in a vertical direction, the height levels occupied by the top and bottom surfaces of a nanostructure, without physical intersection.
For the purposes of examination, the examiner will treat claim met as long as at least one nanostructure and semiconductor structure are next to each other.
Claims 2-9 are rejected as being dependent on Claim 1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9, 11, 12, 14, 16, 18 and 19 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Ching et al. (US 20170005195 A1).
Regarding Claim 1, Ching (Fig. 20-49) discloses a semiconductor device structure, comprising:
a substrate (202);
a plurality of nanostructures (left bottom and middle 306) over the substrate (202);
a semiconductor structure (entire right 306 column) over the substrate (202), wherein
the semiconductor structure (right 306 column) passes through a top and a bottom of at least one of the nanostructures (left bottom 306);
an isolation structure (602) surrounding a lower portion (a fin extending from 202 under right 306 column surrounded by 602) of the semiconductor structure (right 306 column); and
a metal gate stack (4710, 4706) wrapped around the nanostructures (left 306) and a portion of the semiconductor structure (right 306), wherein
the metal gate stack comprises a gate dielectric layer (4706), the gate dielectric layer has a first portion wrapped around a bottommost nanostructure (bottom most left 306) of the nanostructures (left 306) and a second portion extending along a top surface of the isolation structure (602), and the first portion is in direct contact with the second portion. (See Fig. 36, 49A)
Regarding Claim 2, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 1, wherein
topmost surfaces of the nanostructures (left bottom and middle 306) and the semiconductor structure (right 306 column) are at different height levels. (Fig.
Regarding Claim 3, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 1, wherein
a topmost surface of the nanostructures (left bottom and middle 306) is closer to the substrate (202) than a topmost surface of the semiconductor structure (right 306 column).
Regarding Claim 4, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 1, wherein
the metal gate stack (4710,4706) further comprises a work function layer, and the work function layer is prevented from being between a bottommost surface of the nanostructures and the substrate by the gate dielectric layer.
Regarding Claim 5, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 1, wherein
the semiconductor structure (right 306 column) comprises a protruding portion (portion of 202 and 306 above 602) above the lower portion of the semiconductor structure (a fin extending from 202 under right 306 column surrounded by 602).
Regarding Claim 6, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 5, wherein
a bottommost surface of the nanostructures (left bottom and middle 306) is as high as a bottommost surface of the protruding portion of the semiconductor structure (right 306 column).
Regarding Claim 7, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 5, wherein
the metal gate stack (4710,4706) is wrapped around the protruding portion of the semiconductor structure (right 306 column).
Regarding Claim 9, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 8, wherein
the gate dielectric layer (4706) is in direct contact with a bottommost surface of the protruding portion of the semiconductor structure (portion of 202 and 306 above 602) and a topmost surface of the lower portion of the semiconductor structure (a fin extending from 202 under right 306 column surrounded by 602).
Regarding Claim 11, Ching (Fig. 20-49) discloses a semiconductor device structure, comprising:
a substrate (202);
a plurality of nanostructures (left bottom and middle 306) over the substrate (202);
a semiconductor structure (right 306 column) over the substrate (202), wherein
topmost surfaces of the semiconductor structure (right 306 column) and the nanostructures (left bottom and middle 306) are at different height levels (Fig. 20-49);
an isolation structure (602) surrounding a lower portion of the semiconductor structure (a fin extending from 202 under right 306 column surrounded by 602) ; and
a gate stack (4710, 4706) wrapped around the nanostructures (left bottom and middle 306), wherein
the gate stack comprises a gate dielectric layer (4706), and the gate dielectric layer is continuously wrapped around a bottommost nanostructure (bottom left 306) of the nanostructures and extending along a top surface of the isolation structure (706).
Regarding Claim 12, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 11, wherein
the gate stack (4710, 4706) is wrapped around the semiconductor structure (right 306 column).
Regarding Claim 14, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 13, wherein
the semiconductor structure comprises a protruding portion (portion of 202 above 602), a portion of the gate dielectric layer (4706) is between the protruding portion and the lower portion of the semiconductor structure. (portion of 202 above 602)
Regarding Claim 16, Ching (Fig. 20-49) discloses a semiconductor device structure, comprising:
a substrate (202);
a plurality of nanostructures (left bottom and middle 306) over the substrate (202);
a semiconductor fin (a fin extending from 202 under left 306 surrounded by 602) between the substrate (202) and the nanostructures (left bottom and middle 306);
an isolation structure (602) laterally surrounding a lower portion of the semiconductor fin (a fin extending from 202 under right 306 column surrounded by 602), wherein
the semiconductor fin (a fin extending from 202 under right 306 column surrounded by 602) has a protruding portion protruding (portion of 202 above 602) above a top surface of the isolation structure (602); and
a gate stack (4710, 4706) wrapped around the nanostructures, wherein
the gate stack (4710, 4706) comprises a gate dielectric layer (4706), and the gate dielectric layer (4706) continuously extends along a bottommost nanostructure of the nanostructures (left bottom 306) and the protruding portion of the semiconductor fin (portion of 202 above 602).
Regarding Claim 18, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 16, further comprising
a semiconductor structure (right 306 column) over the substrate (202), wherein the gate stack (4710, 4706) is wrapped around the semiconductor structure (right 306 column).
Regarding Claim 19, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 18, wherein
a topmost surface of one nanostructure of the nanostructures (left middle 306) is vertically between a topmost surface and a bottommost surface of the semiconductor structure (right 306 column).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 20170005195 A1) view of Xie et al. (US 10,332,803 B1)
Regarding Claim 10, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 1, wherein
Ching does not explicitly disclose a continuous portion of the semiconductor structure passes through a top and a bottom of each of the nanostructures.
Xie (Fig. 23) discloses a continuous portion of a semiconductor structure (1350) passes through a top and a bottom of each of the nanostructures (1320).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure in Ching in view of Xie such that a continuous portion of the semiconductor structure passes through a top and a bottom of each of the nanostructures in order to have fins with a greater height than nanosheet stack for adjusting channel space [column 15, lines 10-27]
Claim(s) 8, 13, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 20170005195 A1).
Regarding Claim 8, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 7
Ching does not explicitly disclose the metal gate stack further comprises a work function layer, and the work function layer is prevented from being between a bottommost surface of protruding portion of the semiconductor structure and the substrate by the gate dielectric layer.
However, Ching discloses multilayer metal gate stack comprising work function metal layer [0062] and that dielectric layer occupies the space between a bottommost surface of protruding portion of the semiconductor structure and substrate (202)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure in Ching such that the metal gate stack further comprises a work function layer, and the work function layer is prevented from being between a bottommost surface of protruding portion of the semiconductor structure and the substrate by the gate dielectric layer in order to provide a suitable work function for a device type (N or P) [0100, 0118]
Regarding Claim 13, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 11, wherein
Ching does not explicitly disclose the gate stack further comprises a work function layer, the gate dielectric layer is between the nanostructures and the work function layer, and the work function layer is prevented from being between a bottommost surface of the nanostructures and the substrate by the gate dielectric layer.
However, Ching discloses multilayer metal gate stack comprising work function metal layer [0062] and that dielectric layer occupies the space between a bottommost surface of the nanostructures and the substrate by the gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure in Ching such that the gate stack further comprises a work function layer, the gate dielectric layer is between the nanostructures and the work function layer, and the work function layer is prevented from being between a bottommost surface of the nanostructures and the substrate by the gate dielectric layer in order to provide a suitable work function for a device type (N or P) [0100, 0118]
Regarding Claim 15, Ching (Fig. 20-49) discloses the semiconductor device structure as claimed in claim 14.
Ching does not explicitly disclose the work function layer is prevented from being between a bottommost surface of the protruding portion of the semiconductor structure and the substrate by the gate dielectric layer.
However, Ching discloses multilayer metal gate stack comprising work function metal layer [0062] and that dielectric layer occupies the space between a bottommost surface of the protruding portion of the semiconductor structure and the substrate by the gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure in Ching such that the work function layer is prevented from being between a bottommost surface of the protruding portion of the semiconductor structure and the substrate by the gate dielectric layer in order to provide a suitable work function for a device type (N or P) [0100, 0118]
Regarding Claim 17, Ching (Fig. 20-49) discloses a semiconductor device structure as claimed in claim 16, wherein
Ching does not explicitly disclose the gate stack further comprises a work function layer, the gate dielectric layer is between the work function layer and the nanostructures, and the work function layer is prevented from being between a bottommost surface of the nanostructures and the semiconductor fin by the gate dielectric layer.
However, Ching discloses multilayer metal gate stack comprising work function metal layer [0062] and that dielectric layer occupies the space between a bottommost surface of the nanostructures and the semiconductor fin by the gate dielectric layer..
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure in Ching such that he gate stack further comprises a work function layer, the gate dielectric layer is between the work function layer and the nanostructures, and the work function layer is prevented from being between a bottommost surface of the nanostructures and the semiconductor fin by the gate dielectric layer in order to provide a suitable work function for a device type (N or P) [0100, 0118].
Allowable Subject Matter
Claim 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regards to claim 20, none of the prior art teaches or suggests, alone or in combination “a second semiconductor fin between the substrate and the semiconductor structure, wherein the gate dielectric layer completely fills a gap between the second semiconductor fin and the semiconductor structure.” in the combination required by the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rodder et al. (US 2018/0114727 A1) discloses GAA nanostructures with gate dielectric between substrate and bottom most nanostructure.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
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