Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Abstract
The abstract of the disclosure is objected to under 37 C.F.R. § 1.72(b) because it is directed entirely to a method of forming n-type and p-type epitaxy regions, whereas pending claims 1–20 are directed exclusively to semiconductor structures.
In particular, the abstract does not adequately describe the presently claimed structural arrangement, including an n-type source/drain region and a p-type source/drain region, a dielectric fin disposed between the source/drain regions, a dielectric mask contacting the dielectric fin, and a contact etch stop layer contacting the dielectric fin. The abstract therefore does not enable the Office and the public to determine quickly, from a cursory inspection, the nature and gist of the presently claimed technical disclosure.
Furthermore, “an n-type Fin Field-Effect (FinFET) region” should be changed to “an n-type fin field-effect transistor (FinFET) region.”.
A corrected abstract directed to the disclosed semiconductor structure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Specification
The specification is objected to because of the following informalities:
In paragraph [0010], “may have selective loss defect” should be changed to “may have a selective-loss defect” or “may have selective-loss defects.”
2. In paragraph [0014], “filling the recessing with a dielectric material” should be changed to “filling the recess with a dielectric material.”
3. In paragraph [0014], “a high etching selectivity with relative to the materials” should be changed to “a high etching selectivity relative to the materials.”
4. In paragraph [0015], the sentence beginning with “The seam 28 may be caused” should be revised to read as follows:
“The seam 28 may be caused by conformal deposition of the dielectric material, such that portions of the dielectric material deposited on opposite sidewalls of the trench grow toward each other, eventually leaving seam 28 due to premature sealing of the remaining trench.”
5. In paragraph [0018], “In above-illustrated embodiments” should be changed to “In the above-illustrated embodiments.”
6. In paragraph [0019], “one (or a plurality of) hard mask layer 36” should be changed to “one hard mask layer 36 (or a plurality of hard mask layers 36).”
7. In paragraph [0021], “resulting recesses 40 to be formed” should be changed to “resulting in recesses 40 being formed.”
8. In paragraph [0024], “is referred to as dummy fins 25′D hereinafter” should be changed to “is referred to as dummy fin 25′D hereinafter.”
9. In paragraph [0024], “For distinguishing purpose” should be changed to “For distinguishing purposes.”
10. In paragraph [0024], “width W1′, W2′, and W3′ may be substantially equal to each other” should be changed to “widths W1′, W2′, and W3′ may be substantially equal to each other.”
11. In paragraph [0029], “silicon phosphorous (SiP), silicon carbon phosphorous (SiCP)” should be changed to “silicon phosphorus (SiP), silicon carbon phosphorus (SiCP).” Further, the two subsequent occurrences of “phosphorous” should be changed to “phosphorus.”
12. In paragraph [0030], “results in the semiconductor material to be grown” should be changed to “results in the semiconductor material being grown.”
13. In paragraph [0030], “the semiconductor material are adversely grown” should be changed to “the semiconductor material is adversely grown.”
14. In paragraph [0030], “but less-effective in removing the p-type selective-loss defect” should be changed to “but are less effective in removing the p-type selective-loss defect.”
15. In paragraph [0034], “the point where epitaxy regions 42N meets the corresponding dielectric fins 25′N” should be changed to “the point where epitaxy regions 42N meet the corresponding dielectric fins 25′N.”
16. In paragraph [0034], “spaced apart from it neighboring epitaxy region 42N” should be changed to “spaced apart from its neighboring epitaxy region 42N.”
17. In paragraph [0035], “formed of the same or similar material as, and may have the similar structure as, etching mask 48” should be changed to “formed of the same material as, or a material similar to, etching mask 48, and may have a structure similar to that of etching mask 48.”
18. In paragraph [0039], “may be adversely lost and result in the epitaxy material to grow” should be changed to “may be adversely lost and result in the epitaxy material growing.”
19. In paragraph [0040], “the p-type selective-loss defects will grow rather than eliminated” should be changed to “the p-type selective-loss defects will grow rather than be eliminated.”
20. In paragraph [0041], “The remaining of etching mask 56” should be changed to “The remaining portion of epitaxy mask 56.” Element 56 is identified elsewhere in the specification as an epitaxy mask, rather than an etching mask.
21. In paragraph [0043], “There may exists the relationship W2 > W3 > W1” should be changed to “There may exist the relationship W2 > W3 > W1.”
22. In paragraph [0044], “dielectric strips 25′P and 25′N” should be changed to “dielectric fins 25′P and 25′N” for consistency with the terminology used elsewhere in the specification and drawings.
23. In paragraph [0050], both occurrences of “sourced/drain regions” should be changed to “source/drain regions.”
23. In paragraph [0051], “The second shape is a chamfer-shape” should be changed to “The second shape is a chamfered shape.”
24. In paragraph [0054], “after the removing the first epitaxy mask” should be changed to “after removing the first epitaxy mask.”
25. In paragraph [0054], “formed of a same dielectric material” should be changed to “formed of the same dielectric material.”
26. In paragraph [0055], “an n-type source/drain region aside the first gate stack” and “a p-type source/drain region aside the second gate stack” should be changed to “an n-type source/drain region on a side of the first gate stack” and “a p-type source/drain region on a side of the second gate stack,” respectively.
Appropriate correction of the foregoing informalities is required.
Claim Objections
Claims 1, 3, 4, 7, 9, 11, 14, and 18 are objected to because of the following informalities:
1. Claim 1 recites “an n-type Fin Field-Effect (FinFET) region.” The term “FinFET” is an abbreviation for “fin field-effect transistor.” Accordingly, the limitation should be amended to recite “an n-type fin field-effect transistor (FinFET) region.”
2. Claim 1 recites “an n-type source/drain region aside the first gate stack” and “a p-type source/drain region aside the second gate stack.” The term “aside” is not properly used to define the relative spatial positions of the source/drain regions and the respective gate stacks. For example, the limitations may be amended to recite “an n-type source/drain region on a side of the first gate stack” and “a p-type source/drain region on a side of the second gate stack.”
3. Claim 3 recites “a second dielectric material same as the first dielectric material.” The limitation should be amended to recite “a second dielectric material that is the same as the first dielectric material.”
4. Claim 4 recites “a second dielectric fin on an opposite side of the n-type source/drain region than the first dielectric fin.” The phrase “on an opposite side . . . than” does not properly express the intended spatial relationship. For example, the limitation may be amended to recite “a second dielectric fin on a side of the n-type source/drain region opposite the first dielectric fin.”
5. Claim 7 recites “a second dielectric fin on an opposite side of the p-type source/drain region than the first dielectric fin.” For example, the limitation may be amended to recite “a second dielectric fin on a side of the p-type source/drain region opposite the first dielectric fin.”
6. In claim 9, “the dielectric mask further contacts a top surface of the second dielectric fin” appears to contain an incorrect element designation.
Claim 9 depends from claim 7, which recites that the second dielectric fin is disposed on a side of the p-type source/drain region opposite the first dielectric fin and that the contact etch stop layer contacts a sidewall of the second dielectric fin. As illustrated in FIG. 16B, contact etch stop layer 70 appears to contact the sidewalls and top surface of the p-type-side dielectric fin, whereas the remaining portion of epitaxy mask 56 is principally illustrated on dielectric fins in the n-type FinFET region and on the side of dividing dielectric fin 25′D facing the n-type FinFET region.
Accordingly, it appears that Applicant may have intended claim 9 to recite:
“The structure of claim 7, wherein the contact etch stop layer further contacts a top surface of the second dielectric fin.”
Applicant is requested to amend claim 9 accordingly or otherwise clarify that the recited “dielectric mask” is intentional. If the recitation is intentional, Applicant should identify the disclosed dielectric-mask portion, such as a remaining portion of epitaxy mask 46 or 56, that supports the claimed contact with the top surface of the second dielectric fin.
7. Claim 11 recites “The structure of claim 1 further comprises.” To maintain proper dependent-claim form, “further comprises” should be amended to “further comprising.”
8. Claim 14 recites “a n-type source/drain region.” The limitation should be amended to recite “an n-type source/drain region.”
9. Claim 18 recites “an n-type source/drain region aside of the first gate stack” and “a p-type source/drain region aside of the second gate stack.” The term “aside of” is not properly used to define the relative spatial positions of the source/drain regions and the respective gate stacks. For example, the limitations may be amended to recite “an n-type source/drain region on a side of the first gate stack” and “a p-type source/drain region on a side of the second gate stack.”
10. Claim 18 further recites “a second dielectric fin on an opposing side of the n-type source/drain region than the first dielectric fin” and “a third dielectric fin on an opposing side of the p-type source/drain region than the first dielectric fin.” The phrase “on an opposing side . . . than” does not properly express the intended spatial relationships. For example, the limitations may be amended to recite “a second dielectric fin on a side of the n-type source/drain region opposite the first dielectric fin” and “a third dielectric fin on a side of the p-type source/drain region opposite the first dielectric fin.”
Appropriate correction of the foregoing informalities is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,154,974 (“Pat-974”). Although the claims at issue are not identical, they are not patentably distinct from each other:
Regarding claim 1, Claims 1 and 4 of Pat-974 teach the claimed structure. Claim 1 of Pat-974 teaches an n-type FinFET region and a p-type FinFET region; an n-type FinFET comprising a first semiconductor fin, a first gate stack on the first semiconductor fin, and an n-type source/drain region aside the first gate stack; and a p-type FinFET comprising a second semiconductor fin, a second gate stack on the second semiconductor fin, and a p-type source/drain region aside the second gate stack. Claim 1 of Pat-974 further teaches a dielectric mask and a contact etch stop layer.
Furthermore, Claim 4 of Pat-974, which depends from claim 1, further teaches a third dielectric fin between the n-type FinFET region and the p-type FinFET region, the dielectric mask being on a first sidewall of the third dielectric fin facing the n-type FinFET region, and the contact etch stop layer physically contacting a second sidewall of the third dielectric fin facing the p-type FinFET region. Because the n-type and p-type source/drain regions are respectively located in the n-type and p-type FinFET regions, the third dielectric fin positioned between those regions teaches the claimed dielectric fin between the n-type source/drain region and the p-type source/drain region, with its first and second sidewalls respectively facing the n-type and p-type source/drain regions. The dielectric mask on the first sidewall teaches the claimed first portion of the dielectric mask contacting the first sidewall, and the contact etch stop layer physically contacting the second sidewall teaches the claimed contact etch stop layer contacting the second sidewall.
The “third dielectric fin” of claim 4 of Pat-974 teaches the “first dielectric fin” of instant claim 1 because the different ordinal designations merely identify the respective dielectric fins and do not establish a structural distinction. The additional dielectric fins and other elements recited in claims 1 and 4 of Pat-974 do not patentably distinguish instant claim 1 because instant claim 1 uses the open-ended transitional term “comprising” and does not exclude additional structural elements. Therefore, instant claim 1 is not patentably distinct from claims 1 and 4 of Pat-974.
Regarding claim 14, claims 10 and 14 of Pat-974 teach the claimed structure. Claim 10 of Pat-974 teaches a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; and first n-type and first p-type source/drain regions higher than top surfaces of the plurality of isolation regions.
Furthermore, Claim 14 of Pat-974, which depends from claim 10, further teaches a third dielectric fin between the first n-type source/drain region and the first p-type source/drain region, wherein a dielectric mask is on a first sidewall of the third dielectric fin facing the first n-type source/drain region. The “third dielectric fin” of claim 14 of Pat- 974 teaches the “first dielectric fin” of instant claim 14 because the different ordinal designations merely identify the respective dielectric fins and do not establish a structural distinction. The dielectric mask on the first sidewall of the third dielectric fin contacts the third dielectric fin and includes a portion between the first n-type source/drain region and the third dielectric fin, thereby teaching the claimed dielectric mask contacting the first dielectric fin and comprising a first portion between the n-type source/drain region and the first dielectric fin.
The additional source/drain regions and dielectric fins recited in claims 10 and 14 of Pat-974 do not patentably distinguish instant claim 14 because instant claim 14 uses the open-ended transitional term “comprising” and does not exclude additional structural elements. Therefore, instant claim 14 is not patentably distinct from claims 10 and 14 of Pat-974.
Allowable Subject Matter
Claims 1 and 14 would be allowable if overcome the nonstatutory double patenting rejection.
Regarding claim 1, Lin et al. (US 20190103304; in the IDS on 7/30/24; “Lin”) teaches n-type and p-type FinFET regions, n-type and p-type epitaxial source/drain regions 82, dielectric dummy fins 62 separating adjacent epitaxial source/drain regions, and a generally disclosed contact etch stop layer (FIGS. 14A–15C; paragraphs [0043]–[0049]).
And, Ching et al. (US 20190067444; in the IDS on 7/30/24; “Ching”) similarly teaches n-type and p-type FinFET devices, dielectric dummy fin structures 116, p-type epitaxy layers 132, n-type epitaxy layers 136, temporary AlOx masking layer 130, and contact etch stop layer 140 (FIGS. 3A–3C and 9A–12C; paragraphs [0034], [0043]–[0044], and [0056]–[0070]).
However, neither Lin nor Ching, alone or in combination, teaches or suggests a dielectric fin positioned between n-type and p-type source/drain regions, with a dielectric mask contacting the sidewall of the dielectric fin facing the n-type source/drain region and a contact etch stop layer contacting the opposite sidewall of the same dielectric fin facing the p-type source/drain region. Ching expressly removes temporary AlOx masking layer 130 before forming the n-type epitaxy layers and therefore does not provide the claimed residual dielectric-mask structure.
Regarding claim 14, Lin et al. (US 20190103304; in the IDS on 7/30/24; “Lin”) teaches a semiconductor substrate, isolation regions, raised n-type and p-type epitaxial source/drain regions, and dielectric dummy fins separating adjacent source/drain regions.
And Ching et al. (US 20190067444; in the IDS on 7/30/24; “Ching”) teaches dielectric dummy fin structures and temporary masking of the n-type FinFET region during formation of the p-type epitaxy layers.
However, neither Lin nor Ching teaches or suggests a dielectric mask remaining in the completed structure in contact with a dielectric fin positioned between an n-type source/drain region and a p-type source/drain region, with a portion of the dielectric mask specifically positioned between the n-type source/drain region and the dielectric fin. Ching’s temporary AlOx masking layer 130 is removed before formation of the n-type epitaxy layers, and Lin does not disclose the claimed residual dielectric-mask portion.
Accordingly, claims 1 and 14, and dependent claims 2–13 and 15–17, would be in condition for allowance upon overcoming the applicable nonstatutory double-patenting rejection and correcting the outstanding formal objections.
Claims 18–20 are allowable over the prior art and are not subject to the nonstatutory double-patenting rejection over Pat-974.
Regarding claim 18, Lin et al. (US 20190103304; in the IDS on 7/30/24; “Lin”) teaches semiconductor fins, gate stacks, n-type and p-type source/drain regions, and multiple dielectric dummy fins that may separate adjacent epitaxial source/drain regions.
And Ching et al. (US 20190067444; in the IDS on 7/30/24; “Ching”) similarly teaches n-type and p-type FinFET devices, multiple dielectric dummy fin structures 116, temporary epitaxy-masking layers, and contact etch stop layer 140.
However, neither Lin nor Ching, alone or in combination, teaches or suggests the claimed three-dielectric-fin structure having a first dielectric fin between the n-type and p-type source/drain regions, a second dielectric fin on the side of the n-type source/drain region opposite the first dielectric fin, a third dielectric fin on the side of the p-type source/drain region opposite the first dielectric fin, a dielectric mask contacting both the first and second dielectric fins, and a contact etch stop layer contacting the third dielectric fin.
Even assuming that the dielectric fins of the references could be arranged in the claimed three-fin spatial sequence, the references do not teach or suggest the claimed selective contact pattern in which the same dielectric mask contacts the dividing dielectric fin and the n-type-side dielectric fin, while the contact etch stop layer contacts the p-type-side dielectric fin. Ching removes its temporary AlOx masking layer 130 before forming the n-type epitaxy layers, and Lin does not disclose a residual dielectric mask contacting the claimed pair of dielectric fins.
Dependent claims 19 and 20 incorporate the limitations of claim 18 and recite additional limitations not supplied by the prior art. Accordingly, claims 18–20 would be in condition for allowance upon correction of the outstanding formal objections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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