DETAILED ACTION
This action is responsive to the following communications: the Application filed July 30, 2024. This application is a DIV of 17/685,188 filed 03/02/2022.
Claims 1-20 are pending. Claims 1, 11 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dudeck et al. (US 2008/0025103).
Regarding independent claim 1, Dudeck et al. disclose a method of operating a memory device (see e.g., FIG. 1), comprising:
providing, during a read operation (108, OUT, and para 0017: an output signal OUT, i.e., data out at a read operation) of a memory cell of a memory array (103), a first voltage (RSN=“H”) to a control signal line (RSP/RSN, see FIG. 2 for the waveforms of RSP and RSN) connected to a discharge circuit (N2) and a charge sharing circuit (111);
discharging a programmable bit line (110, dummy bit line, i.e., functions as claimed programmable bit line) with the discharge circuit (N2) based on the first voltage (RSN=”H”) on the control signal line (RSP/RSN);
providing a second voltage (RSP=”H”) different from the first voltage to the control signal line (RSP/RSN); and
connecting a bit line (102) to the programmable bit line (110) based on the second voltage (RSP=”H”) on the control signal line (RSP/RSN) (see e.g., FIGS. 1-2, and accompanying disclosure).
Regarding claim 2, which depends from claim 1, Dudeck et al. disclose pre-charging (e.g., FIG. 1: P1) the bit line prior to activating the charge sharing control signal line.
Regarding claim 5, which depends from claim 1, Dudeck et al. disclose the bit line has a first length, and the programmable bit line has a second length (see FIG. 1 or FIG. 3).
Regarding claim 6, which depends from claim 5, Dudeck et al. disclose the first length and second length are the same (see FIG. 1, 102 and 110 length to 111).
Regarding claim 7, which depends from claim 5, Dudeck et al. disclose the first length and second length are different (see FIG. 1, 102 length to 108 and 110 length to 111).
Regarding claim 10, which depends from claim 1, Dudeck et al. disclose the discharge circuit includes an n-type transistor (FIG. 1: N2) including a gate terminal connected to the control signal line (RSP/RSN).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 8-9 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Dudeck et al. (US 2008/0025103).
Regarding claim 3, Dudeck et al. teach the limitations of claim 2.
Dudeck et al. are silent with respect to tracking the bit line to output a tracking signal.
However, tracking bit line to output a tracking signal is an inherent characteristic of memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a tracking signal in memory devices because these conventional technology are well established in the art of the memory devices.
Regarding claim 4, Dudeck et al. teach the limitations of claim 3.
Dudeck et al. further teach the pre-charging (FIG. 1: P1) of the bit line (102) is activated based on a pre-charge control signal (RSP), and wherein the charge sharing control signal (111) is generated based on the tracking signal and the pre-charge control signal (RSP).
Dudeck et al. are silent with respect to tracking the bit line to output a tracking signal.
However, tracking bit line to output a tracking signal is an inherent characteristic of memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a tracking signal in memory devices because these conventional technology are well established in the art of the memory devices.
Regarding claim 8, Dudeck et al. teach the limitations of claim 5.
Dudeck et al. do not explicitly disclose the second length is determined based on a size of the memory array.
However, the length of bit line determined based on a size of the memory array is an inherent characteristic of memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize length of bit lines based on a size of a memory array because these conventional technology are well established in the art of the memory devices.
Regarding claim 9, Dudeck et al. teach the limitations of claim 1.
Dudeck et al. are further teach the charge sharing circuit (FIG. 1: 111) includes a p-type transistor including a gate terminal connected to the control signal line (RSP/RSN).
However, charge sharing circuit including a p-type transistor in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Bringivijayaraghavan et al. (US 2019/0147924), e.g., FIG. 2: P3 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize p-type transistor charge sharing circuit because these conventional technology are well established in the art of the memory devices.
Claims 11-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Dudeck et al. (US 2008/0025103) in view of e.g., Bringivijayaraghavan et al. (US 2019/0147924).
Regarding independent claim 11, Dudeck et al. teach a method of operating a memory device (see e.g., FIG. 1), comprising:
providing, during a read operation (108, OUT, and para 0017: an output signal OUT, i.e., data out at a read operation) of a memory cell of a memory array (103), a first voltage (RSN=“H”) to a control signal line (RSP/RSN, see FIG. 2 for the waveforms of RSP and RSN) connected to a discharge circuit (N2) and a charge sharing circuit (111);
discharging a programmable bit line (110, dummy bit line, i.e., functions as claimed programmable bit line) with the discharge circuit (N2) based on the first voltage (RSN=”H”) on the control signal line (RSP/RSN);
providing a second voltage (RSP=”H”) different from the first voltage to the control signal line (RSP/RSN); and
connecting a bit line (102) to the programmable bit line (110) based on the second voltage (RSP=”H”) on the control signal line (RSP/RSN) (see e.g., FIGS. 1-2, and accompanying disclosure);
wherein the charge sharing circuit (111) includes a p-type transistor including a gate terminal connected to the control signal line, and the discharge circuit includes an n-type transistor (N2) including a gate terminal connected to the control signal line (RSP/RSN).
Dudeck et al. are further teach the charge sharing circuit (FIG. 1: 111) includes a p-type transistor including a gate terminal connected to the control signal line (RSP/RSN).
However, charge sharing circuit including a p-type transistor in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Bringivijayaraghavan et al. (US 2019/0147924), e.g., FIG. 2: P3 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bringivijayaraghavan et al. to the teaching of Dudeck et al. such that a memory, as taught by Dudeck et al., utilizes a transistor, as taught by Bringivijayaraghavan et al., for the purpose of enhancing signal processing to transfer high supply voltage signals, further these conventional technology are well established in the art of the memory devices.
Regarding claim 12, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claim 11.
Dudeck et al. further teach pre-charging (FIG. 1: P1) the bit line prior to activating the charge sharing control signal line (see FIGS. 1-2).
Regarding claims 13 and 20, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claims 12 and 19, respectively.
Dudeck et al. are silent with respect to tracking the bit line to output a tracking signal.
However, tracking bit line to output a tracking signal is an inherent characteristic of memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a tracking signal in memory devices because these conventional technology are well established in the art of the memory devices.
Regarding claim 14, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claim 13.
Dudeck et al. further teach the pre-charging (FIG. 1: P1) of the bit line (102) is activated based on a pre-charge control signal (RSP), and wherein the charge sharing control signal (111) is generated based on the tracking signal and the pre-charge control signal (RSP).
Dudeck et al. are silent with respect to tracking the bit line to output a tracking signal.
However, tracking bit line to output a tracking signal is an inherent characteristic of memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a tracking signal in memory devices because these conventional technology are well established in the art of the memory devices.
Regarding claim 15, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claim 11.
Dudeck et al. further teach the bit line has a first length, and the programmable bit line has a second length (see FIG. 1 or FIG. 3).
Regarding claim 16, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claim 15.
Dudeck et al. further teach the first length and second length are the same (see FIG. 1, 102 and 110 length to 111).
Regarding claim 17, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claim 15.
Dudeck et al. further teach the first length and second length are different (see FIG. 1, 102 length to 108 and 110 length to 111).
Regarding claim 18, Dudeck et al. and Bringivijayaraghavan et al., as combined, teach the limitations of claim 15.
Dudeck et al. do not explicitly disclose the second length is determined based on a size of the memory array.
However, the length of bit line determined based on a size of the memory array is an inherent characteristic of memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize length of bit lines based on a size of a memory array because these conventional technology are well established in the art of the memory devices.
Regarding independent claim 19, Dudeck et al. disclose a method of operating a memory device (see e.g., FIG. 1), comprising:
providing, during a read operation (108, OUT, and para 0017: an output signal OUT, i.e., data out at a read operation) of a memory cell of a memory array (103), a first voltage (RSN=“H”) to a control signal line (RSP/RSN, see FIG. 2 for the waveforms of RSP and RSN) connected to a discharge circuit (N2) and a charge sharing circuit (111);
discharging a programmable bit line (110, dummy bit line, i.e., functions as claimed programmable bit line) with the discharge circuit (N2) based on the first voltage (RSN=”H”) on the control signal line (RSP/RSN);
providing a second voltage (RSP=”H”) different from the first voltage to the control signal line (RSP/RSN);
connecting a bit line (102) to the programmable bit line (110) based on the second voltage (RSP=”H”) on the control signal line (RSP/RSN); and
pre-charging (P1) the bit line prior to activating the charge sharing control signal line (see e.g., FIGS. 1-2, and accompanying disclosure);
wherein the charge sharing circuit (111) includes a p-type transistor including a gate terminal connected to the control signal line, and the discharge circuit includes an n-type transistor (N2) including a gate terminal connected to the control signal line (RSP/RSN).
Dudeck et al. are further teach the charge sharing circuit (FIG. 1: 111) includes a p-type transistor including a gate terminal connected to the control signal line (RSP/RSN).
However, charge sharing circuit including a p-type transistor in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Bringivijayaraghavan et al. (US 2019/0147924), e.g., FIG. 2: P3 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Bringivijayaraghavan et al. to the teaching of Dudeck et al. such that a memory, as taught by Dudeck et al., utilizes a transistor, as taught by Bringivijayaraghavan et al., for the purpose of enhancing signal processing to transfer high supply voltage signals, further these conventional technology are well established in the art of the memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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