DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-18, 21-23, and 28-34 are rejected under 35 U.S.C. 103 as being obvious over US 20090296498 A1 Nakadai et al hereafter “Nakadai”, and in further view of US 9042149 B2 Lee et al hereafter “Lee”
Claim 16 Nakadai a method for manufacturing a memory device, comprising:
disposing a first memory cell (column 0 fig. 10-11), a second memory cell (column 1 fig. 10), a third memory cell (column 2 fig. 10-11) and a fourth memory cell (column 3 fig. 10-11) sequentially along a first direction (0-3 sequence left to right of fig. 10-11) [Paragraph 0028-0029 sufficiently discloses the columns as 1 bit and 4 bit memory cells];
disposing a first conductive (1st wiring layer of VDD fig. 8-9 of column 0 and column 1 fig. 10-11) segment extending in the first direction, where in wherein the first conductive segment is coupled to the first memory cell and the second memory cell [sufficiently illustrated fig. 8-10];
disposing a second conductive segment (2nd wiring layer of column 0 and column 1 VDD fig. 9-10) extending in a second direction different (top to bottom of fig. 9-10) from the first direction between the first memory cell and the second memory cell, wherein the second conductive segment is coupled to the first conductive segment [sufficiently illustrated fig. 9-10 wherein they are coupled by a through hole and/or via];
coupling a first word line (WL1 fig. 10) extending in the first direction to the first memory cell [sufficiently illustrated fig. 10]; and
coupling a second word line (WL2 fig. 10) extending in the first direction to the second memory cell and the fourth memory cell [sufficiently illustrated fig. 11].
coupling a third word line (WL3 fig. 11) extending in the first direction to the third memory cell [sufficiently illustrated fig. 11].
coupling a fourth word line (WL4 fig. 11) extending in the first direction to the fourth memory cell [sufficiently illustrated fig. 11].
Nakadai does not teach coupling a first word line extending in the first direction to the first memory cell and the third memory cell; and
coupling a second word line extending in the first direction to the second memory cell and the fourth memory cell.
Lee teaches a first word line (wl_a fig. 9) extending in a first direction (left to right of fig. 9) to a first memory cell (501 fig. 9) and a third memory cell (501’ fig. 9) [col_A memory cells]; and
coupling a second word line (wl_b fig. 9) extending in the first direction to a second memory cell (502 fig. 9) and the fourth memory cell (502’ fig. 9) [col_B memory cells].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai in view of Lee such that “ coupling a first word line extending in the first direction to the first memory cell and the third memory cell; and coupling a second word line extending in the first direction to the second memory cell and the fourth memory cell”.
A person of ordinary skill in the art would have been motivated to make this modification to reduce the number of word lines required [sufficiently illustrated fig. 9 lee compared to fig. 10-11 Nakadai], and/or to enable the disclosed single-ended read operation and the differential write operation disclose that avoids waste energy during the read operation [Lee column 8 lines 16-31].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining known world line layouts in a memory cell array for the known purposes of electrically addressing and operating memory cells.
Note: in view of the modification of Lee WL0 and WL2 of Nakadai will be treated as a single worldline with interpreting the figures and WL1 and WL3 of Nakadai will also be treated as a single wordline.
Claim 17 Nakadai in view of Lee teaches as shown above the method of claim 16, wherein the first conductive segment crosses over and coupled to each of a first active area (diffusion layer comprising but not limited to Tr3 and/or Tr4 fig. 8 of column 0 fig 10-11) in the first memory cell and a second active area in the first memory cell, and
the second conductive segment is disposed between and separated from the first active area and the second active area [sufficiently illustrated fig. 8-9 VDD 2nd wiring layer is spatially separated from the first active area comprising the diffusion layer further comprising TR3 and/or Tr4 by the first conductive segment and VDD through holes].
Claim 18 Nakadai view of Lee teaches as shown above the method of claim 16, further comprising:
disposing a third conductive segment (VDD 1st wiring layer fig. 8-9 of columns 2 and 3 fig. 10-11) extending in the first direction, wherein the third conductive segment is coupled to the third memory cell and the fourth memory cell [sufficiently illustrated fig. 10 in view of fig. 8-9]; and
disposing a fourth conductive segment (VDD 2nd wiring layer fig. 9-10 of columns 2 and 3 fig. 10-11) extending in the second direction between the third memory cell and the fourth memory cell, wherein the fourth conductive segment is coupled to the third conductive segment [sufficiently illustrated fig. 9, coupled by VDD through hole and/or via].
Claim 21 Nakadai a method, comprising:
forming a first memory cell (MC column 0 fig. 3 and column 0 fig. 10-11), a second memory cell (MC column 1 fig. 3 and column 1 fig. 10-11), a third memory cell (MC column 2 fig. 3 and column 2 fig. 10-11) and a fourth memory cell (MC column 3 fig. 3 and column 3 fig. 10-11) arranged sequentially along a first direction [left to right of fig. 3, 10-11];
forming a first conductive segment (VDD 1st wiring layer fig. 8-9 of columns 0 and 1 fig. 3, 10-11) coupled to the first memory cell and the second memory cell and disposed between a boundary between the first memory cell and the second memory cell [sufficiently illustrated 8-9 in view of fig. 10-11];
forming a second conductive segment (VDD 1st wiring layer fig. 8-9 of columns 2 and 3 fig. 3, 10-11) coupled to the third memory cell and the fourth memory cell and disposed between a boundary between the third memory cell and the fourth memory cell [sufficiently illustrated 8-9 in view of fig. 10-11];
forming a first word line (WL1 fig. 10) crossing over each of the first conductive segment and the second conductive segment [sufficiently illustrated fig. 10], and coupled the first memory cell [sufficiently illustrated fig. 11]; and
forming a second word line (WL2 fig. 10) crossing over each of the first conductive segment and the second conductive segment [sufficiently illustrated fig. 11 in view of fig. 10], and coupled to each of the second memory cell [sufficiently illustrated3 fig. 11].
forming a third word line (WL3 fig. 11) crossing over each of the first conductive segment and the second conductive segment [sufficiently illustrated fig. 11 in view of fig. 10], and coupled the third memory cell [sufficiently illustrated fig. 11]; and
forming a fourth word line (WL4 fig. 11) crossing over each of the first conductive segment and the second conductive segment [sufficiently illustrated fig. 11 in view of fig. 10], and coupled the fourth memory cell [sufficiently illustrated fig. 11];
Nakadai does not teach coupling the first word line to the first memory cell and the third memory cell; and
coupling the second word line to the second memory cell and the fourth memory cell.
Lee teaches a first word line (wl_a fig. 9) extending in a first direction (left to right of fig. 9) to a first memory cell (501 fig. 9) and a third memory cell (501’ fig. 9) [col_A memory cells]; and
coupling a second word line (wl_b fig. 9) extending in the first direction to a second memory cell (502 fig. 9) and the fourth memory cell (502’ fig. 9) [col_B memory cells].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai in view of Lee such that “ forming a first word line crossing over each of the first conductive segment and the second conductive segment, and coupled to each of the first memory cell and the third memory cell; and forming a second word line crossing over each of the first conductive segment and the second conductive segment, and coupled to each of the second memory cell and the fourth memory cell.” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to reduce the number of word lines required [sufficiently illustrated fig. 9 lee compared to fig. 10-11 Nakadai], and/or to enable the disclosed single-ended read operation and the differential write operation disclose that avoids waste energy during the read operation [Lee column 8 lines 16-31].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this case it is combining known world line layouts in a memory cell array for the known purposes of electrically addressing and operating memory cells.
Note: in view of the modification of Lee WL0 and WL2 of Nakadai will be treated as a single worldline with interpreting the figures and WL1 and WL3 of Nakadai will also be treated as a single wordline.
Claim 22 Nakadai view of Lee teaches as shown above the method of claim 21, further comprising:
forming a first via (through hole of WL 3rd wiring layer column 0 fig. 10) coupled between the first word line and the first memory cell [sufficiently illustrated fig. 10 in view of fig. 11 which illustrates WL 3rd wiring layer column 0 being part of WL2];
forming a second via (through hole of WL 3rd wiring layer WL2 column 2 fig. 11) coupled between the first word line and the third memory cell; and
forming a third via (through hole of WL 3rd wiring layer column 1 fig. 10) coupled between the second word line and the second memory cell [sufficiently illustrated fig. 10 in view of fig. 11 which illustrates WL 3rd wiring layer column 1 being part of WL3], and disposed between the first via and the second via along the first direction [sufficiently illustrated fig. 11-12].
Claim 23 Nakadai view of Lee teaches as shown above the method of claim 22, further comprising:
forming a fourth via (through hole WL 3rd wiring layer WL3 fig. 11) coupled between the second word line and the fourth memory cell [sufficiently illustrated fig. 11],
wherein the second via is disposed between the third via and the fourth via along the first direction [sufficiently illustrated fig. 10-11].
Claim 28 Nakadai view of Lee teaches as shown above the method of claim 21, wherein the first conductive segment is configured to transmit a reference voltage signal to each of the first memory cell which coupled to the first word line and the second memory cell which coupled to the second word line [VDD sufficiently disclosed a reference voltage in “power supply voltage” Nakadai Paragraph 0047) and/or met under MPEP 2112.01 the structure is structurally and/or compositionally the same as disclosed thus this functional limitation is met and/or the device is considered at least capable of performing the function].
Claim 29 Nakadai view of Lee The method of claim 28, wherein the second conductive segment is configured to transmit the reference voltage signal to each of the third memory cell which coupled to the first word line and the fourth memory cell which coupled to the second word line [VDD sufficiently disclosed a reference voltage in “power supply voltage” Nakadai Paragraph 0047) and/or met under MPEP 2112.01 the structure is structurally and/or compositionally the same as disclosed thus this functional limitation is met and/or the device is considered at least capable of performing the function].
Claim 30 Nakadai teaches as shown above a method, comprising:
forming a first memory cell (MC column 0 fig. 10-11 in view of fig. 3), a second memory cell (MC column 1 fig. 10-11 in view of fig. 3), a third memory cell (MC column 2 fig. 10-11 in view of fig. 3) and a fourth memory cell (MC column 3 fig. 10-11 in view of fig. 3) arranged sequentially along a first direction [left to right of fig. 10-11];
forming a first via group (WL through holes of column 0 fig. 10-11) coupled to the first memory cell;
forming a second via group (WL through holes of column 1 fig. 10-11) coupled to the second memory cell;
forming a third via group (WL through holes of column 2 fig. 10-11) coupled to the third memory cell;
forming a fourth via group (WL through holes of column 3 fig. 10-11) coupled to the fourth memory cell;
forming a first word line (WL1 fig. 10) extending along the first direction and coupled to the first via group; and
forming a second word line (WL2 fig. 10) extending along the first direction and coupled to the second via group,
forming a third word line (WL3 fig. 10) extending along the first direction and coupled to the third via group,
forming a fourth word line (WL4 fig. 10) extending along the first direction and coupled to the fourth via group,
wherein the first via group, the second via group, the third via group, and the fourth via group are arranged alternately along the first direction [sufficiently illustrated fig. 10-11].
Lee teaches forming a first via group (910 and 915 fig. 9) coupled to a first memory cell and a third memory cell (501 and 501’ fig. 9);
forming a second via group (920 and 925 fig. 9) coupled to a second memory cell and a fourth memory cell (502 and 502’)
forming a first word line (wl_a fig. 9) extending along a first direction [left to right fig. 9] and coupled to the first via group; and
forming a second word line (wl_b fig. 9) extending along the first direction and coupled to the second via group;
wherein the first via group and the second via group are arranged alternately along the first direction [sufficiently illustrated fig. 9].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai in view of Lee such that “forming a first via group coupled to the first memory cell and the third memory cell; forming a second via group coupled to the second memory cell and the fourth memory cell; forming a first word line extending along the first direction and coupled to the first via group; and forming a second word line extending along the first direction and coupled to the second via group, wherein the first via group and the second via group are arranged alternately along the first direction” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to reduce the number of word lines required [sufficiently illustrated fig. 9 lee compared to fig. 10-11 Nakadai], and/or to enable the disclosed single-ended read operation and the differential write operation disclose that avoids waste energy during the read operation [Lee column 8 lines 16-31].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this case it is combining known world line layouts in a memory cell array for the known purposes of electrically addressing and operating memory cells.
Note: in view of the modification of Lee WL0 and WL2 of Nakadai will be treated as a single worldline with interpreting the figures and WL1 and WL3 of Nakadai will also be treated as a single wordline.
Claim 31 Nakadai view of Lee teaches as shown above the method of claim 30, further comprising:
forming a first conductive segment (VDD 1st wiring layer fig. 8-9 of columns 0 and 1 fig. 3, 10-11) coupled to the first memory cell and the second memory cell and disposed between a boundary between the first memory cell and the second memory cell [best illustrated fig. 10];
and forming a second conductive segment (VDD 1st wiring layer fig. 8-9 of columns 2 and 3 fig. 3, 10-11) coupled to the third memory cell and the fourth memory cell and disposed between a boundary between the third memory cell and the fourth memory cell [best illustrated fig. 10].
Claim 32 Nakadai view of Lee teaches as shown above the method of claim 31, wherein the first conductive segment is configured to transmit a reference voltage signal to each of the first memory cell which coupled to the first word line and the second memory cell which coupled to the second word line [VDD sufficiently disclosed a reference voltage in “power supply voltage” Nakadai Paragraph 0047) and/or met under MPEP 2112.01 the structure is structurally and/or compositionally the same as disclosed thus this functional limitation is met and/or the device is considered at least capable of performing the function].
Claim 33 Nakadai view of Lee teaches as shown above the method of claim 32, wherein the second conductive segment is configured to transmit the reference voltage signal to each of the third memory cell which coupled to the first word line and the fourth memory cell which coupled to the second word line [VDD sufficiently disclosed a reference voltage in “power supply voltage” Nakadai Paragraph 0047) and/or met under MPEP 2112.01 the structure is structurally and/or compositionally the same as disclosed thus this functional limitation is met and/or the device is considered at least capable of performing the function].
Claim 34 Nakadai view of Lee teaches as shown above the method of claim 30, wherein forming the first via group and forming the second via group comprise:
forming a first via (WL through hole contacting WL2 2nd wiring layer column 0 fig. 10 in view of fig. 11) coupled between the first word line and the first memory cell [sufficiently illustrated fig. 10-11];
forming a second via (WL through hole contacting WL2 2nd wiring layer column 2 fig. 10 in view of fig. 11) coupled between the first word line and the third memory cell;
forming a third via WL through hole contacting WL2 2nd wiring layer column 1 fig. 10 in view of fig. 11) coupled between the second word line and the second memory cell, and disposed between the first via and the second via along the first direction [sufficiently illustrated fig. 10-11]; and
forming a fourth via (WL through hole contacting WL2 2nd wiring layer column 3 fig. 10 in view of fig. 11) coupled between the second word line and the fourth memory cell, wherein
the second via is disposed between the third via and the fourth via along the first direction.
Claims 24-27, and 35 are rejected under 35 U.S.C. 103 under 35 U.S.C. 103 as obvious over Nakadai view of Lee as shown above.
Claim 24 Nakadai view of Lee teaches as shown above the method of claim 22, further comprising:
forming a fourth via (top left WL Contact hole between 1st wiring layer and polysilicon layer of Tr1 fig. 8, see annotation below) coupled to a first gate structure (polysilicon layer crossing TR1 fig. 8) of the first memory cell; and
forming a fifth via (bottom right WL Contact hole between 1st wiring layer and polysilicon layer of Tr1 fig. 8, see annotation below) coupled to a second gate structure (polysilicon layer crossing TR2 fig. 8) of the first memory cell,
wherein the first via is disposed between the fourth via and the fifth via along a second direction (top to bottom of fig. 8-11) different from the first direction [met under broadest reasonable interpretation, illustrated in the combination of fig. 8, 9, 10, 11 see annotation below, note the first via appears to positioned in the center of the memory cell along the second direction fig. 10-11, the fourth via appears to be near the top and/or first quarter of the memory cell along the second direction fig. 8 and 9, and the fifth appears to be near the bottom of the memory cell and/or fourth quarter along the second direction fig. 8 and 9].
In the alternative Nakadai also teaches in fig. 5 an identical memory cell circuit to the memory cell circuit as illustrated fig. 1, 4A, 5, and 6A, and 7 of the instant application; wherein Tr1 Nakadai matches T11 instant application, Tr2 Nakadai matches T12, Tr3 matches P11, TR4 matches P12, Tr5 matches S11, TR6 matches S12, VSS matches VSS, VDD matches VDD, BL and /BL matches BL11 and B12, WL matches WL 11 and fig. 5 similarly matches all the other Memory cells as illustrated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai such that “the first via is disposed between the fourth via and the fifth via along a second direction different from the first direction”.
A person of ordinary skill in the art would have been motivated to make this modification as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI C.]
PNG
media_image1.png
609
913
media_image1.png
Greyscale
Annotated fig. 8: highlighting the relative positions of the first, fourth and fifth vias in view of fig. 10
Claim 25 Nakadai view of Lee teaches as shown above the method of claim 24, further comprising:
forming a third conductive segment (WL 2nd wiring layer fig. 8-11) coupled to the first word line through the first via [illustrated fig. 10 in view of fig. 11, in view of Lee], and coupled to the first memory cell through the fourth via and the fifth via [illustrated fig. 9 in view of fig. 8].
Claim 26 Nakadai view of Lee teaches as shown above the method of claim 22, further comprising:
forming a third conductive segment (1st wiring layer BL and/or /BL fig. 8-9) coupling a bit line (2nd wiring layer BL and/or /BL fig. 9-10) to the first memory cell; and
forming a fourth conductive segment (polysilicon layer opposing 1st wiring layer BL and/or /Bl fig. 8 in the first direction) coupled to a control terminal of a switch (gate of Tr3 and Tr5 and/or gate of Tr4 and Tr6 ) in the first memory cell,
wherein the first via is disposed between the third conductive segment and the fourth conductive segment along the first direction [met under broadest reasonable interpretation, see annotation below].
In the alternative Nakadai also teaches in fig. 5 an identical memory cell circuit to the memory cell circuit as illustrated fig. 1, 4A, 5, and 6A, and 7 of the instant application; wherein Tr1 Nakadai matches T11 instant application, Tr2 Nakadai matches T12, Tr3 matches P11, TR4 matches P12, Tr5 matches S11, TR6 matches S12, VSS matches VSS, VDD matches VDD, BL and /BL matches BL11 and B12, WL matches WL 11 and fig. 5 similarly matches all the other Memory cells as illustrated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai view of Lee such that “the first via is disposed between the third conductive segment and the fourth conductive segment along the first direction”.
A person of ordinary skill in the art would have been motivated to make this modification as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI C.]
PNG
media_image2.png
677
843
media_image2.png
Greyscale
Annotated fig. 8: highlighting positions of a fourth conductive segment, a third conductive segment, and a first via along the first direction as measured from a left most edge.
PNG
media_image3.png
677
843
media_image3.png
Greyscale
Annotated fig. 8: highlighting positions of a fourth conductive segment, a third conductive segment, and a first via along the first direction as measured from a right most edge.
Claim 27 Nakadai view of Lee teaches as shown above the method of claim 26, wherein the fourth conductive segment is disposed between the first via and the second via along the first direction [met under broadest reasonable interpretation at least a portion of the conductive segment is disposed between the first via and the second via along the first direction in view of fig. 8-11, see annotation below].
In the alternative Nakadai view of Lee also teaches in fig. 5 an identical memory cell circuit to the memory cell circuit as illustrated fig. 1, 4A, 5, and 6A, and 7 of the instant application; wherein Tr1 Nakadai matches T11 instant application, Tr2 Nakadai matches T12, Tr3 matches P11, TR4 matches P12, Tr5 matches S11, TR6 matches S12, VSS matches VSS, VDD matches VDD, BL and /BL matches BL11 and B12, WL matches WL 11 and fig. 5 similarly matches all the other Memory cells as illustrated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai such that “the fourth conductive segment is disposed between the first via and the second via along the first direction”.
A person of ordinary skill in the art would have been motivated to make this modification as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI C.]
PNG
media_image4.png
506
1726
media_image4.png
Greyscale
Annotated fig. 10: highlighting the relative positions of a first via, a second via and the fourth conductive segment.
Claim 35 Nakadai view of Lee as shown above teaches the method of claim 34, further comprising:
forming a fifth via (top left WL Contact hole between 1st wiring layer and polysilicon layer of Tr1 fig. 8) coupled to a first gate structure (polysilicon layer of Tr1 fig. 8) of the first memory cell;
forming a sixth via (bottom right WL Contact hole between 1st wiring layer and polysilicon layer of Tr2 fig. 8, see annotation below)) coupled to a second gate structure (polysilicon layer of Tr2 fig. 8) of the first memory cell; and
forming a conductive segment (WL 1st and/or 2nd wiring layer fig. 8-9 in view of fig. 10-11) coupled to the first word line through the first via, and coupled to the first memory cell through the fifth via and the sixth via,
wherein the first via is disposed between the fifth via and the sixth via along a second direction different from the first direction [sufficiently illustrated fig. 8-9 in view of fig. 10-11 see annotation below].
In the alternative Nakadai also teaches in fig. 5 an identical memory cell circuit to the memory cell circuit as illustrated fig. 1, 4A, 5, and 6A, and 7 of the instant application; wherein Tr1 Nakadai matches T11 instant application, Tr2 Nakadai matches T12, Tr3 matches P11, TR4 matches P12, Tr5 matches S11, TR6 matches S12, VSS matches VSS, VDD matches VDD, BL and /BL matches BL11 and B12, WL matches WL 11 and fig. 5 similarly matches all the other Memory cells as illustrated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai such that “the first via is disposed between the fifth via and the sixth via along a second direction different from the first direction”.
A person of ordinary skill in the art would have been motivated to make this modification as rearrangement of parts is prima facie type obviousness [See MPEP 2144.04 VI C.]
PNG
media_image5.png
609
913
media_image5.png
Greyscale
Annotated fig. 8: highlighting the relative positions of a fifth, sixth, and first vias in view of fig. 10-11
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakadai in view of Lee as applied to the claims above, and further in view of US 9177619 B2 Kajigaya et al hereafter “Kajigaya”.
Claim 19 Nakadai in view of Lee teaches the method of claim 18, further comprising: a read circuit (14 fig. 1 and/or 34 fig. 3) connected configured to read each of the first memory cell, the second memory cell, the third memory cell and the fourth memory cell [sufficiently illustrated fig. 1 and fig. 3]; further comprising a sense amplifier (50 fig. 14, and 150 fig. 15)
Nakadai in view of Lee does not teach disposing a read circuit between the second memory cell and the third memory cell.
Kajigaya teaches disposing a read circuit and/or sense amplifier (LSA fig. 10) between a nth memory cell (left MC fig. 10) and a mth memory cell (Right MC fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nakadai in view of Kajigaya such that “a read circuit between the second memory cell and the third memory cell”.
A person of ordinary skill in the art would have been motivated to make this modification to speed up writing operations [sufficiently disclosed Kajigaya column 9 lines 37-49], improve sensing margin, reduce coupling noise, and/or simplify the manufacturing process [sufficiently Kajigaya disclosed column 11 lines 30-39].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. Combining methods of manufacturing for the purpose of forming random access memory [RAM].
Claim 20 Nakadai in view of Lee and Kajigaya teaches as shown above the method of claim 19, further comprising:
disposing a fifth conductive segment (VSS fig. 10) extending in the first direction between the third conductive segment and the first conductive segment [sufficiently illustrates that at least a portion of VSS is between the first conductive segment and the third conductive segment under broadest reasonable interpretation],
wherein the fifth conductive segment is configured to provide a first reference voltage signal (sufficiently disclosed as “Ground voltage” Nakadai Paragraph 0047) to each of the read circuit [necessarily met in view of the modification of the local sense amplifiers of Kaigaya “ground potential” VSS is connected to LSA illustrated fig. 3 and LSA is between the second and third memory cells], the second memory cell [illustrated fig. 10 Nakadai] and the third memory cell [illustrated fig. 10 Nakadai].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights