DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/30/2024, 08/05/2024, 10/15/2025, 01/21/2026, 04/16/2026, 04/23/2026 and 07/10/2026 was filed after the mailing date of the application on 07/30/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vincent et al, US 20150270233 A1 (Vincent).
Regarding claim 1; Vincent teaches a method for forming a semiconductor device (Vincent: annotated Fig (10) shared in this OA: 130), comprising:
forming a redistribution structure (66) comprising a plurality of layers (layers of 66),
wherein each of the plurality of layers comprises a power/ground plane (134; [0034]: “… dielectric blocks 88 are capped by a solid metal plane, such a power and/or ground plane. This may be appreciated by again referring to FIGS. 9 and 10, which illustrate blocks 88 as capped by solid metal planes 134 and 144, respectively.”) embedded in a dielectric material (38), and
wherein the power/ground plane (134) encloses a plurality of first conductive structures (86) and a plurality of second conductive structures (132) collectively surrounding the plurality of first conductive structures (Looking at Figures (10) and (2) shows that the first conductive structures (86) are surrounded by a plurality of second conductive structures (132) in the same layer (66)); and
attaching the redistribution structure (66) to a first semiconductor die (52) on a first side of the redistribution structure (66) with a plurality of first connectors (86);
wherein the power/ground plane (134) is configured to provide the first semiconductor die (52) with a supply voltage (84 and 86 are connected to each other and connect the power or ground plane 134 to the semiconductor chip 52),
the plurality of first conductive structures (86) are each operatively coupled to the semiconductor die (52), and
the plurality of second conductive (32) structures each have a floating voltage ([0033]: “In certain embodiments, the metal fill features assume the form of floating dummy plates, which are electrically isolated from the interconnect lines surrounding the routing-free dielectric block.”).
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Regarding claim 6; Vincent teaches all the limitations of the method of claim 1.
Vincent teaches wherein the plurality of second conductive structures (Vincent: annotated Fig (10) shared in this OA: 132) are scattered around the plurality of first conductive structures (86).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 2-3, 11-12 and 14are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent).
Regarding claim 2; Vincent teaches all the limitations of the method of claim 1.
Additionally, Vincent teaches, further comprising: attaching the redistribution structure (Vincent: Annotated Fig (10) shared in this OA: 66) to a substrate (annotated Fig (5) shared in this OA: 108) on a second side (Second Side) of the redistribution structure (66) with a plurality of second connectors (68), the second side (Second Side) being opposite to the first side (First Side).
The first embodiment of the device depicted in Fig (5) of Vincent and the second embodiment depicted in Fig (10) are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment by attaching the device to a substrate as disclosed in the second embodiment to provide support for the device and external power sources routing leading to a more reliable device.
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Regarding claim 3; Vincent teaches all the limitations of the method of claim 2.
Vincent teaches wherein the redistribution structure (Vincent: Annotated Fig (10) shared in this OA): 66) is configured to rearrange a first pattern of the plurality of first connectors (86) as a second pattern of the plurality of second connectors (68; examining Fig (10) of Vincent shows that the first connectors 86 are arranged in a pattern that matches the pattern of the first connectors 68).
Regarding claim 11; Vincent teaches a method for forming a semiconductor device (Vincent: annotated Fig (10) shared in this OA: 130), comprising:
forming a redistribution structure (66) comprising a plurality of layers (layers of 66),
wherein each of the plurality of layers comprises a power/ground plane (134; [0034]: “… dielectric blocks 88 are capped by a solid metal plane, such a power and/or ground plane. This may be appreciated by again referring to FIGS. 9 and 10, which illustrate blocks 88 as capped by solid metal planes 134 and 144, respectively.”) embedded in a dielectric material (38), and
wherein the power/ground plane (134) encloses a plurality of first conductive structures (86) and a plurality of second conductive structures (132) collectively surrounding the plurality of first conductive structures (Looking at Figures (10) and (2) shows that the first conductive structures (86) are surrounded by a plurality of second conductive structures (132) in the same layer (66));
attaching the redistribution structure (66) to a first semiconductor die (52) on a first side of the redistribution structure (66) with a plurality of first connectors (86); and
attaching the redistribution structure to a substrate on a second side of the redistribution structure with a plurality of second connectors, the second side being opposite to the first side;
wherein the power/ground plane (134) is configured to provide the first semiconductor die (52) with a supply voltage (84 and 86 are connected to each other and connect the power or ground plane 134 to the semiconductor chip 52),
the plurality of first conductive structures (86) are each operatively coupled to the semiconductor die (52), and
the plurality of second conductive (132) structures each have a floating voltage ([0033]: “In certain embodiments, the metal fill features assume the form of floating dummy plates, which are electrically isolated from the interconnect lines surrounding the routing-free dielectric block.”).
While the first embodiment of Vincent disclosed in Fig (10) teaches a redistribution strcutrue, it does not teach attaching the redistribution structure to a substrate on a second side of the redistribution structure with a plurality of second connectors, the second side being opposite to the first side;
However, the second embodiment of Vincent disclosed in Fig (5) teaches attaching the redistribution structures (66) to a substrate (Annotated Fig (5) shared in this OA: 108) on a second side (Second Side) of the redistribution structure (66) with a plurality of second connectors (68), the second side (Second Side) being opposite to the first side (First Side).
The first and second embodiments of the method of Vincent disclosed in Fig (10) and Fig (5), respectively, are considered analogous embodiments for being methods of constructing a semiconductor device with a redistribution structure. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment of Vincent by attaching the device to a substrate as disclosed in the second embodiment of Vincent to provide support for the device and make connecting with external power sources easier leading to a more reliable device).
Regarding claim 12; Vincent teaches all the limitations of the method of claim 11.
Vincent teaches wherein the redistribution structure (Vincent: Annotated Fig (10) shared in this OA): 66) is configured to rearrange a first pattern of the plurality of first connectors (86) as a second pattern of the plurality of second connectors (68; examining Fig (10) of Vincent shows that the first connectors 86 are arranged in a pattern that matches the pattern of the first connectors 68).
Regarding claim 14; Vincent teaches all the limitations of the method of claim 11.
Vincent teaches wherein the plurality of second conductive structures (Vincent: annotated Fig (10) shared in this OA: 132) are scattered around the plurality of first conductive structures (86).
Claims 4-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Lee et al, US 20210225708 A1 (Lee)
Regarding claim 4; Vincent teaches all the limitations of the method of claim 2.
However, Vincent does not teach further comprising: forming a plurality of third connectors on a first side of the substrate opposite to a second side of the substrate that faces the plurality of second connectors.
Lee teaches further comprising: forming a plurality of third connectors (Lee: Annotated Fig (1S) shared in this OA: 34) on a first side (First Side) of the substrate (Substrate) opposite to a second side (Second Side) of the substrate (Substrate) that faces the plurality of second connectors (36).
Vincent and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the plurality of third connectors as disclosed in Lee to make establishing electrical connections between the semiconductor chip and other components of the device easier leading to a more efficient device production process.
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Regarding claim 5; Vincent teaches all the limitations of the method of claim 1.
However, Vincent does not teach wherein a spacing between neighboring ones of the plurality of first conductive structures is equal to or greater than about 20 micrometers (μm).
Lee teaches teaches wherein a spacing between neighboring ones of the plurality of first conductive structures (Lee: Fig (1I): WBspild) is equal to or greater than about 20 micrometers (μm) ([0009]: “… for example, W.sub.spild is greater than 50, 40 or 30 micrometers, and W.sub.sptsv is smaller than 50, 40 or 30 micrometers.”).
Vincent and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to a person having ordinary skill in the art to modify Vincent to make the spacing between neighboring ones of the first subset of conductive structures to be equal to or greater than about 20 micrometers as disclosed in Lee to minimize the risk of short circuits and cross talk between the conductive structures.
Regarding claim 13; Vincent teaches all the limitations of the method of claim 11.
However, Vincent does not teach wherein a spacing between neighboring ones of the plurality of first conductive structures is equal to or greater than about 20 micrometers (μm).
Lee teaches teaches wherein a spacing between neighboring ones of the plurality of first conductive structures (Lee: Fig (1I): WBspild) is equal to or greater than about 20 micrometers (μm) ([0009]: “… for example, W.sub.spild is greater than 50, 40 or 30 micrometers, and W.sub.sptsv is smaller than 50, 40 or 30 micrometers.”).
Vincent and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to a person having ordinary skill in the art to modify Vincent to make the spacing between neighboring ones of the first subset of conductive structures to be equal to or greater than about 20 micrometers as disclosed in Lee to minimize the risk of short circuits and cross talk between the conductive structures.
Claims 7-10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Liao et al, US 20170203959 A1 (Liao).
Regarding claim 7; Vincent teaches all the limitations of the method of claim 1.
Vincent teaches wherein the power/ground plane (Vincent: annotated Fig (10) shared in this OA: 134) further encloses a guard ring that partially surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Vincent does not teach encloses a guard ring that partially surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Liao teaches further encloses a guard ring (Liao: Annotated Fig (12B) shared in this OA: 23) that partially surrounds the plurality of first conductive structures (First Conductive Structures) and the plurality of second conductive structures (Second Conductive Structures, by examining Fig (12B) it can be seen that some of the guard ring structures 23 partially surround the first and second conductive structures and other fully surround the first and second conductive structures).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
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Regarding claim 8; Vincent in view of Liao teaches all the limitations of the method of claim 7.
Vincent does not teach wherein the guard ring is either connected to or isolated from the power/ground plane.
However, Liao teaches wherein the guard ring (Liao: annotated Fig (12B) shared in this OA: 23) is either connected to or isolated from the power/ground plane (in a device such as the one shown in Fig (5B) there are only two options: 1. A portion of the device (such as a guard ring) is connected to the power/ground contacts through a network of conductors or 2. It is isolated from them. In this case given the absence of mention of such connections in the specification and the drawings of Liao, the examiner is assuming the guard rings 23 are isolated from the power/ground plane/sources. However, if there happens to be connections that are omitted from the diagram in Liao for simplicity, then that would mean that the guard rings are connected to the power/ground contacts through a network of conductors/connections and in that case the guard ring 23 maps correctly with its connections to the claimed limitations).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings to be isolated from the power/ground plane as disclosed in Liao to further ensure the reduction of the possibilities of a short circuit between the different conductive components leading to a more reliable device.
Regarding claim 9; Vincent teaches all the limitations of the method of claim 1.
Vincent teaches wherein the power/ground plane (Vincent: annotated Fig (10) shared in this OA: 134) further encloses a guard ring that fully surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Vincent does not teach further encloses a guard ring that fully surrounds the plurality of first conductive structures and the plurality of second conductive structures.
Liao teaches further encloses a guard ring (Liao: annotated Fig (5B) shared in this OA: 23) that fully surrounds the plurality of first conductive structures (First Conductive Structures) and the plurality of second conductive structures (Second Conductive Structures).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
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Regarding claim 10; Vincent in view of Liao teaches all the limitations of the method of claim 9.
Vincent does not teach wherein the guard ring is either connected to or isolated from the power/ground plane.
However, Liao teaches wherein the guard ring (Liao: annotated Fig (5B) shared in this OA: 23) is either connected to or isolated from the power/ground plane (in a device such as the one shown in Fig (5B) there are only two options: 1. A portion of the device (such as a guard ring) is connected to the power/ground contacts through a network of conductors or 2. It is isolated from them. In this case given the absence of mention of such connections in the specification and the drawings of Liao, the examiner is assuming the guard rings 23 are isolated from the power/ground plane/sources. However, if there happens to be connections that are omitted from the diagram in Liao for simplicity, then that would mean that the guard rings are connected to the power/ground contacts through a network of conductors/connections and in that case the guard ring 23 maps correctly with its connections to the claimed limitations).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings to be isolated from the power/ground plane as disclosed in Liao to further ensure the reduction of the possibilities of a short circuit between the different conductive components leading to a more reliable device.
Regarding claim 15; Vincent teaches all the limitations of the method of claim 11.
Vincent teaches wherein the power/ground plane (Vincent: annotated Fig (10) shared in this OA: 134) further encloses a guard ring that partially surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Vincent does not teach encloses a guard ring that partially surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Liao teaches further encloses a guard ring (Liao: Annotated Fig (12B) shared in this OA: 23) that partially surrounds the plurality of first conductive structures (First Conductive Structures) and the plurality of second conductive structures (Second Conductive Structures, by examining Fig (12B) it can be seen that some of the guard ring structures 23 partially surround the first and second conductive structures and other fully surround the first and second conductive structures).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
Regarding claim 16; Vincent in view of Liao teaches all the limitations of the method of claim 15.
Vincent does not teach wherein the guard ring is either connected to or isolated from the power/ground plane.
However, Liao teaches wherein the guard ring (Liao: annotated Fig (12B) shared in this OA: 23) is either connected to or isolated from the power/ground plane (in a device such as the one shown in Fig (5B) there are only two options: 1. A portion of the device (such as a guard ring) is connected to the power/ground contacts through a network of conductors or 2. It is isolated from them. In this case given the absence of mention of such connections in the specification and the drawings of Liao, the examiner is assuming the guard rings 23 are isolated from the power/ground plane/sources. However, if there happens to be connections that are omitted from the diagram in Liao for simplicity, then that would mean that the guard rings are connected to the power/ground contacts through a network of conductors/connections and in that case the guard ring 23 maps correctly with its connections to the claimed limitations).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings to be isolated from the power/ground plane as disclosed in Liao to further ensure the reduction of the possibilities of a short circuit between the different conductive components leading to a more reliable device.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Masaki et al, JP 2012160763 A (Masaki).
Regarding claim 17; Vincent teaches a method for forming a semiconductor device (Vincent: annotated Fig (10) shared in this OA: 130), comprising:
forming a redistribution structure (66) comprising a plurality of layers (layers of 66),
wherein each of the plurality of layers comprises a power/ground plane (134; [0034]: “… dielectric blocks 88 are capped by a solid metal plane, such a power and/or ground plane. This may be appreciated by again referring to FIGS. 9 and 10, which illustrate blocks 88 as capped by solid metal planes 134 and 144, respectively.”) embedded in a dielectric material (38), and
wherein the power/ground plane (134) encloses a plurality of first conductive structures (86) and a plurality of second conductive structures (132) collectively surrounding the plurality of first conductive structures (Looking at Figures (10) and (2) shows that the first conductive structures (86) are surrounded by a plurality of second conductive structures (132) in the same layer (66));
attaching the redistribution structure (66) to a first semiconductor die (52) on a first side of the redistribution structure (66) with a plurality of first connectors (86); and
attaching the redistribution structure to a substrate on a second side of the redistribution structure with a plurality of second connectors, the second side being opposite to the first side;
wherein the power/ground plane (134) is configured to provide the first semiconductor die (52) with a supply voltage (84 and 86 are connected to each other and connect the power or ground plane 134 to the semiconductor chip 52),
the plurality of first conductive structures (86) are each operatively coupled to the semiconductor die (52) and configured to deliver a signal ([0027]: “…The metal levels are patterned to define electrically-conductive structures including a series of interconnect lines 84, which, along with metal plugs 86, provide electrical communication between semiconductor die 52 and at least one contact array accessible from the exterior of package 60”), and
the plurality of second conductive (132) structures each have a floating voltage ([0033]: “In certain embodiments, the metal fill features assume the form of floating dummy plates, which are electrically isolated from the interconnect lines surrounding the routing-free dielectric block.”) and formed as a dot scattered around the plurality of first conductive structures.
While the first embodiment of Vincent disclosed in Fig (10) teaches a redistribution strcutrue, it does not teach attaching the redistribution structure to a substrate on a second side of the redistribution structure with a plurality of second connectors, the second side being opposite to the first side;
However, the second embodiment of Vincent disclosed in Fig (5) teaches attaching the redistribution structures (66) to a substrate (Annotated Fig (5) shared in this OA: 108) on a second side (Second Side) of the redistribution structure (66) with a plurality of second connectors (68), the second side (Second Side) being opposite to the first side (First Side).
The first and second embodiments of the method of Vincent disclosed in Fig (10) and Fig (5), respectively, are considered analogous embodiments for being methods of constructing a semiconductor device with a redistribution structure. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment of Vincent by attaching the device to a substrate as disclosed in the second embodiment of Vincent to provide support for the device and make connecting with external power sources easier leading to a more reliable device).
Vincent does not teach the plurality of second conductive (132) structures each have a floating voltage formed as a dot scattered around the plurality of first conductive structures.
Makai teaches the plurality of second conductive structures (Masaki: Fig (21): 3) each have a floating voltage (Abstract: “…The body patterns 2 electrically connected to multilayer wiring and the floated dummy patterns 3 are mixed and formed in the surface of the semiconductor substrate 1S”) formed as a dot scattered around the plurality of first conductive structures (2).
Vincent and Masaki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to construct the second conductive structures to have a dot shape and be scattered around the first conductive structures as disclosed in Masaki to establish isolation between the different components of the first conductive structures which reduces the possibility of short circuits or cross talking between the different components of the device leading to a more reliable device.
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Regarding claim 18; Vincent teaches all the limitations of the method of claim 17.
Vincent teaches wherein the redistribution structure (Vincent: Annotated Fig (10) shared in this OA): 66) is configured to rearrange a first pattern of the plurality of first connectors (86) as a second pattern of the plurality of second connectors (68; examining Fig (10) of Vincent shows that the first connectors 86 are arranged in a pattern that matches the pattern of the first connectors 68).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Masaki et al, JP 2012160763 A (Masaki) in further view of Lee et al, US 20210225708 A1 (Lee).
Regarding claim 19; Vincent in view of Masaki teaches all the limitations of the method of claim 17.
However, Vincent does not teach wherein a spacing between neighboring ones of the plurality of first conductive structures is equal to or greater than about 20 micrometers (μm).
Lee teaches wherein a spacing between neighboring ones of the plurality of first conductive structures (Lee: Fig (1I): WBspild) is equal to or greater than about 20 micrometers (μm) ([0009]: “… for example, W.sub.spild is greater than 50, 40 or 30 micrometers, and W.sub.sptsv is smaller than 50, 40 or 30 micrometers.”).
Vincent and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to a person having ordinary skill in the art to modify Vincent to make the spacing between neighboring ones of the first subset of conductive structures to be equal to or greater than about 20 micrometers as disclosed in Lee to minimize the risk of short circuits and cross talk between the conductive structures.
Claims 20 rejected under 35 U.S.C. 103 as being unpatentable over Vincent et al, US 20150270233 A1 (Vincent) in view of Masaki et al, JP 2012160763 A (Masaki) in further view of Liao et al, US 20170203959 A1 (Liao)
Regarding claim 20; Vincent in view of Masaki teaches all the limitations of the method of claim 17.
Vincent teaches wherein the power/ground plane (Vincent: annotated Fig (10) shared in this OA: 134) further encloses a guard ring that partially or fully surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Vincent does not teach encloses a guard ring that partially or fully surrounds the plurality of first conductive structures and the plurality of second conductive structures.
However, Liao teaches further encloses a guard ring (Liao: Annotated Fig (12B) shared in this OA: 23) that partially or fully surrounds the plurality of first conductive structures (First Conductive Structures) and the plurality of second conductive structures (Second Conductive Structures, by examining Fig (12B) it can be seen that some of the guard ring structures 23 partially surround the first and second conductive structures and other fully surround the first and second conductive structures).
Vincent and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Vincent by constructing the guard rings as disclosed in Liao to improve the insulation of the conductive structures and thus reduce the possibilities of short circuits or cross talk in the circuit leading to a more reliable device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Huang et al, US 11107775 B1 (Huang); discloses guard rings surrounding first and second conductive structure patterns.
Lin et al, TW 201804542 A (Lin); discloses conductive patterns on both sides of a substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.K./Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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