DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: The fin-based structure is shown in Fig 23 as 508a and Examiner notes a typographical error in the specification (Para [0076]) where that structure is referenced as 408a.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guha et al. (US 2020/0044087 A1, hereinafter Guha ‘087).
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With respect to Claim 13 Guha ‘087 discloses a method for fabricating a memory device (Fig 1-15), comprising:
forming a first transistor (leftmost transistor shown in annotated Fig 14A_2 of Guha ‘087, Para [0031], hereinafter FBS) in a first region (first region of 300 as shown in annotated Fig 14A_2 of Guha ‘087) of a substrate (300, Fig 14A, Para [0044]), wherein the first transistor (FBS) includes:
a fin-based structure (annotated Fig 14A_2 of Guha ‘087, Para [0031] discloses transistors are formed on subfins) extending along a first physical direction (x direction as shown in annotated Fig 14A_2 of Guha ‘087);
a first gate structure (leftmost 332/334/336, Fig 9A, Para [0070]) extending along a second physical direction (z direction) and straddling the fin-based structure (Fig 9A-9B discloses 334/336 straddling FBS in z direction), the second physical direction (z direction) being perpendicular (shown in axis of Fig 9A) to the first lateral direction (x direction);
a first source/drain (S/D) region (leftmost 360 as shown in annotated Fig 14A_2 of Guha ‘087, Para [0046], hereinafter 1SD) disposed on (1SD on left side of first gate structure shown in annotated Fig 14A_2 of Guha ‘087) a first side (left side of first gate structure) of the first gate structure (leftmost 332/334/336) along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087); and
a second S/D region (second from left 360 as shown in annotated Fig 14A_2 of Guha ‘087, Para [0046], hereinafter 2SD) disposed on (2SD on right side of first gate structure shown in annotated Fig 14A_2 of Guha ‘087) a second side (right side of first gate structure) of the first gate structure (leftmost 332/334/336) along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087);
forming a second transistor (center transistor shown in annotated Fig 14A_2 of Guha ‘087, Para [0031] discloses nanosheet based structure, hereinafter 1NS) in a second region (second region of 300 as shown in annotated Fig 14A_2 of Guha ‘087) of the substrate (300) adjacent (second region adjacent first region shown in annotated Fig 14A_2 of Guha ‘087) the first region (first region of 300 as shown in annotated Fig 14A_2 of Guha ‘087) along the first physical direction(x direction shown in annotated Fig 14A_2 of Guha ‘087), wherein the second transistor (1NS) includes:
a plurality of first nanosheets (312 of 1NS, shown in annotated Fig 14A_2 of Guha ‘087, Para [0047]) extending along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087);
a second gate structure (center 332/334/336, Fig 9A, Para [0070]) extending along the second physical direction (z direction shown in annotated Fig 14A_2 of Guha ‘087) and wrapping around (334/336 wrapping around 312 in z direction disclosed in Fig 9B) each of the plurality of first nanosheets (312 of 1NS);
the second S/D region (2SD) which is on a first side (left side of second gate structure) of the second gate structure (center 332/334/336) along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087); and
a third S/D region (third from left 360 as shown in annotated Fig 14A_2 of Guha ‘087, Para [0046], hereinafter 3SD) on a second side (right side of second gate structure) of the second gate structure (center 332/334/336) along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087); and
forming a third transistor (rightmost transistor shown in annotated Fig 14A_2 of Guha ‘087, Para [0031] discloses nanosheet based structure, hereinafter 2NS) in the second region (second region of 300 as shown in annotated Fig 14A_2 of Guha ‘087) of the substrate (300), wherein the third transistor (2NS) includes:
a plurality of second nanosheets (312 of 2NS, shown in annotated Fig 14A_2 of Guha ‘087, Para [0047]) extending along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087);
a third gate structure (rightmost 332/334/336, Fig 9A, Para [0070]) extending along the second physical direction (z direction shown in annotated Fig 14A_2 of Guha ‘087) and wrapping around (334/336 wrapping around 312 in z direction disclosed in Fig 9B) each of the plurality of second nanosheets (312 of 2NS);
the third S/D region (third from left 360 as shown in annotated Fig 14A_2 of Guha ‘087, Para [0046], hereinafter 3SD) which is on a first side (left side of third gate structure) of the third gate structure (rightmost 332/334/336) along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087); and
a fourth S/D region (rightmost 360 as shown in annotated Fig 14A_2, Para [0046], hereinafter 4SD) on a second side (right side of third gate structure) of the third gate structure (rightmost 332/334/336) along the first physical direction (x direction shown in annotated Fig 14A_2 of Guha ‘087).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 7-8, 10-12, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guha ‘087, in view of the following arguments.
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With respect to Claim 1 Guha ‘087 discloses a method for fabricating a semiconductor device (Fig 1-15), comprising:
forming a fin-based structure (leftmost transistor shown in annotated Fig 14A of Guha ‘087, Para [0031] discloses transistors are formed on subfins, hereinafter FBS) protruding from (FBS protruding from top of 300 disclosed in annotated Fig 14A of Guha ‘087) a top boundary (top of 300 as shown in annotated Fig 14A of Guha ‘087) of a substrate (300, Fig 14A, Para [0044]), wherein the fin-based structure (FBS) is made of a first semiconductor material (Si, Fig 14A, Para [0044] discloses 300 as Si);
forming a first nanosheet-based structure (center transistor shown in annotated Fig 14A of Guha ‘087, Para [0031] discloses nanosheet based structure, hereinafter 1NS) protruding from (1NS protruding from top of 300 disclosed in annotated Fig 14A of Guha ‘087) the top boundary (top of 300 as shown in annotated Fig 14A of Guha ‘087) of the substrate (300), wherein the first nanosheet-based structure (1NS) includes one or more first nanosheets (312 of 1NS, Fig 14A, Para [0047]), made of a second semiconductor material (SiGe, Fig 14A, Para [0052] discloses 312 of 1NS as SiGe), and one or more second nanosheets (311 of 1NS, Fig 7A, Para [0047]), made of the first semiconductor material (Si, Para [0052] discloses 311 of 1NS as Si), the one or more first nanosheets (312 of 1NS) and the one or more second nanosheets (311 of NS) being alternatingly disposed with respect to each other (Fig 7A discloses 311 of 1NS and 312 of 1NS alternately disposed with respect to each other);
epitaxially growing a first source/drain (S/D) region (second from left 360 as shown in annotated Fig 14A of Guha ‘087, Para [0046], hereinafter 1SD), a second S/D region (leftmost 360 as shown in annotated Fig 14A of Guha ‘087, Para [0046], hereinafter 2SD), and a third S/D region (third from left 360 as shown in annotated Fig 14A of Guha ‘087, Para [0046], hereinafter 3SD), wherein the first S/D region (1SD) is disposed between (1SD disposed between FBS and 1NS disclosed in annotated Fig 14A of Guha ‘087) the fin-based structure (FBS) and the first nanosheet-based structure (1NS), the second S/D region (2SD) is disposed opposite (2SD disposed opposite FBS from 1SD disclosed in annotated Fig 14A of Guha ‘087) the fin-based structure (FBS) from the first S/D region (1SD), and the third S/D region (3SD) is disposed opposite (3SD disposed opposite 1NS from 1SD disclosed in annotated Fig 14A of Guha ‘087) the first nanosheet-based structure (1NS) from the first S/D region (1SD), a
forming a second nanosheet-based structure (rightmost transistor shown in annotated Fig 14A of Guha ‘087, Para [0031] discloses nanosheet based structure, hereinafter 2NS) protruding from (2NS protruding from top of 300 disclosed in annotated Fig 14A of Guha ‘087) the boundary (top of 300 as shown in annotated Fig 14A of Guha ‘087) of the substrate (300) and laterally spaced apart from (2NS laterally spaced apart from 1NS disclosed in annotated Fig 14A of Guha ‘087) the first nanosheet-based structure (1NS); and
epitaxially growing a fourth S/D region (rightmost 360 as shown in annotated Fig 14A, Para [0046], hereinafter 4SD), wherein the fourth S/D region (4SD) is disposed opposite (4SD disposed opposite 2NS from 3SD disclosed in annotated Fig 14A of Guha ‘087) the second nanosheet-based structure (2NS) from the third S/D region (3SD).
In an embodiment, (Ref Para [0065] of Guha ‘087), Guha ‘087 teaches and wherein the first to third S/D regions (1SD/2SD/3SD) have a same conductive type (Para [0046] discloses an embodiment where all S/D regions 360 are p-type);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Guha ‘087’s further teaching of the all S/D regions have a same conductive type into Guha ‘087’s device. Guha ‘087 presents several options for doping the substrate and the source and drain regions, including an embodiment wherein the substrate is doped with one conductivity type and the source and drain regions doped in a second conductivity type. The ordinary artisan would have been motivated to modify Guha ‘087 in the manner set forth above, at least, because doping the substrate with one conductivity all the source and drain regions to the same second conductivity would simplify the manufacturing process.
As incorporated, the teaching of the source/drain regions all having the same conductivity as taught by the embodiment of Guha ‘087 would be used as the conductive type of source drain regions in the device of Guha ‘087.
With respect to Claim 4 Guha ‘087 discloses all limitations of the method of claim 1, and Guha ‘087 discloses further comprising:
forming a first gate structure (leftmost 332/334/336, Fig 9A, Para [0070]) straddling the fin-based structure (FBS)(annotated Fig 14A of Guha ‘087 discloses 332/334/336 straddling FBS);
removing (removing 311 of 1NS disclosed in Fig 8A and Para [0069]) the one or more second nanosheets (311 of 1NS); and
forming a second gate structure (center 332/334/336, Fig 9A, Para [0070]) wrapping around (332/334/336 wrapping around 312 of 1NS disclosed in Fig 9B) each of the one or more first nanosheets (312 of 1NS).
With respect to Claim 7 Guha ‘087 discloses all limitations of the method of claim 1, and Guha ‘087 further discloses wherein the second nanosheet-based structure (2NS) includes one or more third nanosheets (312 of 2NS, shown in annotated Fig 14A of Guha ‘087, Para [0047]), made of the first semiconductor material (SiGe, Fig 14A, Para [0052] discloses 312 of 2NS as SiGe), and one or more fourth nanosheets (311 of 2NS, Fig 7A, Para [0047]), made of the second semiconductor material (Si, Para [0052] discloses 311 of 2NS as Si), the one or more third nanosheets (312 of 2NS) and the one or more fourth nanosheets (311 of 2NS) being alternatingly disposed with respect to each other (Fig 7A discloses 311 of 2NS and 312 of 2NS alternately disposed with respect to each other).
With respect to Claim 8 Guha ‘087 discloses all limitations of the method of claim 7, and Guha ‘087 further discloses wherein the first to the fourth S/D regions (1SD/2SD/3SD/4SD) have a same conductive type (as incorporated above the embodiment of Para [0065] of Guha ‘087 discloses S/D regions as the same conductive type).
With respect to Claim 10 Guha ‘087 discloses all limitations of the method of claim 1, wherein the fin-based structure (FBS) and the one or more first nanosheets (312 of 1NS) all extend along a same physical direction (Fig 9A and 9B disclose FBS and 312 of 1NS all extend in the z direction).
With respect to Claim 11 Guha ‘087 discloses all limitations of the method of claim 1, and Guha ‘087 discloses further comprising:
forming the fin-based structure (FBS) in a first region (first region of 300 as shown in annotated Fig 5A of Guha ‘087) of the substrate (300);
forming a recess (recess of second region of 300 shown in Fig 4A and annotated Fig 5A of Guha ‘087) in a second region (second region of 300 as shown in annotated Fig 5A of Guha ‘087) of the substrate (300); and
forming the first nanosheet-based structure (1NS) in the recess (recess of second region of 300 shown in annotated Fig 5A of Guha ‘087).
With respect to Claim 12 Guha ‘087 discloses all limitations of the method of claim 11, and Guha ‘087 discloses further comprising:
covering the fin-based structure (FBS) with a blocking mask (322, Fig 5A and 6A, Para [0055]) while etching (Para [0055] discloses 322 protects during etching process) respective end portions (Fig 6A discloses ends of 311 of 1NS etched) of each of the one or more second nanosheets (311 of 1NS); and
forming a pair of inner spacers (350, Fig 6A, Para [0059]) in contact with each of the one or more etched second nanosheets (312 of 1NS)(Fig 6A disclose 250 contacting 312).
With respect to Claim 16 Guha ‘087 discloses all limitations of the method of claim 13, and in a further embodiment (Ref Para [0065] of Guha ‘087), Guha ‘087 teaches wherein the first to third S/D regions (1SD/2SD/3SD) have a same conductive type (Para [0046] discloses an embodiment where all S/D regions 360 are p-type).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Guha ‘087’s further teaching of the all S/D regions have a same conductive type into Guha ‘087’s device. Guha ‘087 presents several options for doping the substrate and the source and drain regions, including an embodiment wherein the substrate is doped with one conductivity type and the source and drain regions doped in a second conductivity type. The ordinary artisan would have been motivated to modify Guha ‘087 in the manner set forth above, at least, because doping the substrate with one conductivity all the source and drain regions to the same second conductivity would simplify the manufacturing process.
As incorporated, the teaching of the source/drain regions all having the same conductivity as taught by the embodiment of Guha ‘087 would be used as the conductive type of source drain regions in the device of Guha ‘087.
With respect to Claim 17 Guha ‘087 discloses all limitations of the method of claim 13, wherein the first to the fourth S/D regions (1SD/2SD/3SD/4SD) have a same conductive type (as incorporated above the embodiment of Para [0065] of Guha ‘087 discloses S/D regions as the same conductive type).
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With respect to Claim 19 Guha ‘087 discloses a method for fabricating a semiconductor device (Fig 1-15), comprising:
forming a fin-based structure (leftmost transistor shown in annotated Fig 14A of Guha ‘087, Para [0031] discloses transistors are formed on subfins, hereinafter FBS) protruding from (FBS protruding from top of 300 disclosed in annotated Fig 14A of Guha ‘087) a top boundary (top of 300 as shown in annotated Fig 14A of Guha ‘087) of a substrate (300, Fig 14A, Para [0044];
forming a first nanosheet-based structure (center transistor shown in annotated Fig 14A of Guha ‘087, Para [0031] discloses nanosheet based structure, hereinafter 1NS) protruding from (1NS protruding from top of 300 disclosed in annotated Fig 14A of Guha ‘087) the top boundary (top of 300 as shown in annotated Fig 14A of Guha ‘087) of the substrate (300);
epitaxially growing a first source/drain (S/D) region (second from left 360 as shown in annotated Fig 14A of Guha ‘087, Para [0046], hereinafter 1SD), a second S/D region (leftmost 360 as shown in annotated Fig 14A of Guha ‘087, Para [0046], hereinafter 2SD), and a third S/D region (third from left 360 as shown in annotated Fig 14A of Guha ‘087, Para [0046], hereinafter 3SD), wherein the first S/D region (1SD) is disposed between (1SD disposed between FBS and 1NS disclosed in annotated Fig 14A of Guha ‘087) the fin-based structure (FBS) and the first nanosheet-based structure (1NS), the second S/D region (2SD) is disposed opposite (2SD disposed opposite FBS from 1SD disclosed in annotated Fig 14A of Guha ‘087) the fin-based structure (FBS) from the first S/D region (1SD), and the third S/D region (3SD) is disposed opposite (3SD disposed opposite 1NS from 1SD disclosed in annotated Fig 14A of Guha ‘087) the first nanosheet-based structure (1NS) from the first S/D region (1SD),
forming a second nanosheet-based structure (rightmost transistor shown in annotated Fig 14A of Guha ‘087, Para [0031] discloses nanosheet based structure, hereinafter 2NS) protruding from (2NS protruding from top of 300 disclosed in annotated Fig 14A of Guha ‘087) the boundary (top of 300 as shown in annotated Fig 14A of Guha ‘087) of the substrate (300) and laterally spaced apart from (2NS laterally spaced apart from 1NS disclosed in annotated Fig 14A of Guha ‘087) the first nanosheet-based structure (1NS); and
epitaxially growing a fourth S/D region (rightmost 360 as shown in annotated Fig 14A, Para [0046], hereinafter 4SD), wherein the fourth S/D region (4SD) is disposed opposite (4SD disposed opposite 2NS from 3SD disclosed in annotated Fig 14A of Guha ‘087) the second nanosheet-based structure (2NS) from the third S/D region (3SD).
In an embodiment, (Ref Para [0065] of Guha ‘087), Guha ‘087 teaches and wherein the first to third S/D regions (1SD/2SD/3SD) have a same conductive type (Para [0046] discloses an embodiment where all S/D regions 360 are p-type);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Guha ‘087’s further teaching of the all S/D regions have a same conductive type into Guha ‘087’s device. Guha ‘087 presents several options for doping the substrate and the source and drain regions, including an embodiment wherein the substrate is doped with one conductivity type and the source and drain regions doped in a second conductivity type. The ordinary artisan would have been motivated to modify Guha ‘087 in the manner set forth above, at least, because doping the substrate with one conductivity all the source and drain regions to the same second conductivity would simplify the manufacturing process.
As incorporated, the teaching of the source/drain regions all having the same conductivity as taught by the embodiment of Guha ‘087 would be used as the conductive type of source drain regions in the device of Guha ‘087.
With respect to Claim 20 Guha ‘087 discloses all limitations of the method of claim 19, and Guha ‘087 further discloses wherein the fin-based structure (FBS) is made of a first semiconductor material (Si, Fig 14A, Para [0044] discloses 300 as Si), and wherein the first nanosheet-based structure (1NS) includes one or more first nanosheets (312 of 1NS, as shown in annotated Fig 14A of Guha ‘087, Para [0047]), made of a second semiconductor material (SiGe, Fig 14A, Para [0052] discloses 312 of 1NS as SiGe), and one or more second nanosheets (311 of 1NS, Fig 7A, Para [0047]), made of the first semiconductor material (Si, Para [0052] discloses 311 of 1NS as Si), the one or more first nanosheets (312 of 1NS) and the one or more second nanosheets (311 of 1NS) being alternatingly disposed with respect to each other (Fig 7A discloses 311 of 1NS and 312 of 1NS alternately disposed with respect to each other).
Allowable Subject Matter
Claims 2-3, 5-6, 9, 14-15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 1 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein sidewalls of the fin-based structure each have a first crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane”.
Regarding Claim 3, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 1 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein the first crystal plane includes a {110} crystal plane, and the second crystal plane incudes a {100} crystal plane”.
Regarding Claim 5, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 4 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein the first gate structure, the fin-based structure, the first S/D region, and the second S/D region collectively operate as a programming transistor of an anti-fuse memory cell, and the second gate structure, the one or more first nanosheets, the second S/D region, and the third S/D region collectively operate as a reading transistor of the anti-fuse memory cell”.
Regarding Claim 6, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 4 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein the reading transistor is electrically coupled to the programming transistor in series via the second S/D region”.
Regarding Claim 9, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 1 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein sidewalls of the fin-based structure each have a first crystal plane, a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane, and a top boundary and a bottom boundary of each of the one or more third nanosheets have the second crystal plane, and wherein the first crystal plane includes a {110} crystal plane, and the second crystal plane incudes a {100} crystal plane”.
Regarding Claim 14, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 13 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein sidewalls of the fin-based structure each have a first crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane”.
Regarding Claim 15, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 13 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein sidewalls of the fin-based structure each have a first crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane”.
Regarding Claim 18, Allowable subject matter has been indicated because the closest prior art of record Guha ‘087 teaches the limitations of Claim 13 but Guha ‘087, fails to teach or fairly suggest the feature: “wherein the first transistor operatively functions as a programming transistor of an anti-fuse memory cell, wherein the second transistor operatively functions as a first reading transistor of the anti-fuse memory cell, and wherein the third transistor operatively functions as a second reading transistor of the anti-fuse memory cell”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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