DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/28/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 14-15 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12-13 and 15 of U.S. Patent No. 11,699,736. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 14, Pat '736 discloses, in claims 12 and 15, a method, comprising: forming a first dielectric layer over a first channel; forming a first work function metal layer over the first dielectric layer; forming a first protection layer over the first work function metal layer; forming a second protection layer over the first protection layer (all limitations are the same with the limitations recited in claim 12 of Pat '736); forming a glue layer over the second protection layer; and forming a first metal layer over the glue layer ("forming a glue layer over the second protection layer, wherein the first metal fill layer is formed over the glue layer", in claim 15 of Pat '736, is interpreted as the same limitation).
Regarding claim 15, Pat '736 discloses the method of claim 14 as described above.
Pat '736 further discloses, in claim 13, forming a third protection layer over the first protection layer and the second protection layer before forming the first metal layer ("forming a third protection layer over the second protection layer before forming the first metal fill layer", in claim 13 of Pat '736, is interpreted as the same limitation).
Regarding claim 19, Pat '736 discloses the method of claim 14 as described above.
Pat '736 further discloses, in claims 12 and 15, forming an interfacial layer over the first channel, wherein the first dielectric layer is formed over the interfacial layer; and forming a capping layer over the first work function metal layer, wherein the first protection layer and the second protection layer are formed over the capping layer (“forming a second protection layer over the first protection layer” and "forming an interfacial layer over the first channel, wherein the first dielectric layer is formed over the interfacial layer; forming a capping layer over the first work function metal layer, wherein the first protection layer is formed over the capping layer", in claims 12 and 15 of Pat '736, are interpreted as the same limitation).
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 4-13 of U.S. Patent No. 12,100,748 in view of claim 15 of U.S. Patent No. 11,699,736.
Regarding claim 1, Pat '748 discloses, in claims 1 and 3, a device, comprising: a stack of semiconductor nanostructures over a substrate; and a gate structure over and wrapping around the semiconductor nanostructures, including: a first dielectric layer over the semiconductor nanostructures; a first work function metal layer over the first dielectric layer; a first protection layer over the first work function metal layer (all limitations are the same with the limitations recited in claim 1 of Pat '748); a second protection layer over the first protection layer (all limitations are the same with the limitations recited in claim 3 of Pat '748).
Pat '748 does not explicitly disclose a glue layer over the second protection layer; and a metal layer over the glue layer.
Pat '736 teaches, in claim 15, a glue layer over the second protection layer; and a metal layer over the glue layer ("forming a glue layer over the second protection layer, wherein the first metal fill layer is formed over the glue layer", in claim 15 of Pat '736, is interpreted as the same limitation), for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '748 to have the glue layer over the second protection layer; the metal layer over the glue layer, as taught by Pat '736, for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Regarding claim 2, Pat '748 in view of Pat '736 discloses the device of claim 1 as described above.
Pat '748 further discloses, in claim 2, the gate structure further comprises a barrier layer between the first work function metal layer and the first dielectric layer (all limitations are the same with the limitations recited in claim 2 of Pat '748).
Regarding claim 3, Pat '748 in view of Pat '736 discloses the device of claim 1 as described above.
Pat '748 further discloses, in claim 1, the gate structure further comprises a capping layer physically contacting the first protection layer and the first work function metal layer ("a capping layer in physical contact with the first protection layer and the first work function metal layer", in claim 1 of Pat '748, is interpreted as the same limitation).
Regarding claim 4, Pat '748 in view of Pat '736 discloses the device of claim 1 as described above.
Pat '748 further discloses, in claim 4, the gate structure further comprises the gate structure further comprises a third protection layer over the second protection layer (all limitations are the same with the limitations recited in claim 4 of Pat '748).
Regarding claim 5, Pat '748 in view of Pat '736 discloses the device of claim 1 as described above.
Pat '748 further discloses, in claim 5, the first protection layer comprises Si, Ge, SiGe, Al, Ti, or Hf; and the second protection layer comprises a metal or a conductive metal oxide (all limitations are the same with the limitations recited in claim 5 of Pat '748).
Regarding claim 6, Pat '748 in view of Pat '736 discloses the device of claim 1 as described above.
Pat '748 further discloses, in claim 6, the gate structure further comprises: an interfacial layer between the first dielectric layer and the semiconductor nanostructures (all limitations are the same with the limitations recited in claim 6 of Pat '748).
Regarding claim 6, Pat '748 in view of Pat '736 discloses the device of claim 1 as described above.
Pat '748 further discloses, in claim 7, the gate structure wraps around a first semiconductor nanostructure and a second semiconductor nanostructure of the stack, the second semiconductor nanostructure being between the first semiconductor nanostructure and the substrate (all limitations are the same with the limitations recited in claim 7 of Pat '748).
Regarding claim 8, Pat '748 discloses, in claim 8, a device, comprising: a first gate structure, including: a first dielectric layer over a first semiconductor nanostructure; a first work function metal layer over the first dielectric layer; at least two first protection layers over the first work function metal layer; and a second gate structure including: a second dielectric layer over a second semiconductor nanostructure; a first barrier layer over the second dielectric layer; a second work function metal layer over the first barrier layer; at least one second protection layer over the second work function metal layer; and a second metal layer over the at least one second protection layer (all limitations are the same with the limitations recited in claim 8 of Pat '748).
Pat '748 does not explicitly disclose a glue layer over the at least two first protection layers; a first metal layer over the glue layer.
Pat '736 teaches, in claims 12 and 15, a glue layer over the at least two first protection layers; a first metal layer over the glue layer (“forming a second protection layer over the first protection layer” and "forming a glue layer over the second protection layer, wherein the first metal fill layer is formed over the glue layer", in claims 14 and 15 of Pat '736, are interpreted as the same limitation), for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '748 to have the glue layer over the at least two first protection layers; the first metal layer over the glue layer, as taught by Pat '736, for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Regarding claim 9, Pat '748 in view of Pat '736 discloses the device of claim 8 as described above.
Pat '748 further discloses, in claim 9, the first semiconductor nanostructure and the second semiconductor nanostructure are formed in the same material layer (all limitations are the same with the limitations recited in claim 9 of Pat '748).
Regarding claim 10, Pat '748 in view of Pat '736 discloses the device of claim 8 as described above.
Pat '748 further discloses, in claim 10, the first semiconductor nanostructure is silicon and the second semiconductor nanostructure is SiGe (all limitations are the same with the limitations recited in claim 10 of Pat '748).
Regarding claim 11, Pat '748 in view of Pat '736 discloses the device of claim 8 as described above.
Pat '748 further discloses, in claim 11, the first gate structure further comprises a fourth protection layer over the at least two first protection layers (all limitations are the same with the limitations recited in claim 11 of Pat '748).
Regarding claim 12, Pat '748 in view of Pat '736 discloses the device of claim 8 as described above.
Pat '748 further discloses, in claim 12, the at least two first protection layers and the at least one second protection layer are in-situ silane passivation layers (all limitations are the same with the limitations recited in claim 12 of Pat '748).
Regarding claim 13, Pat '748 in view of Pat '736 discloses the device of claim 8 as described above.
Pat '748 further discloses, in claim 13, the second gate structure further comprises a second barrier layer between the first barrier layer and the second work function metal layer (all limitations are the same with the limitations recited in claim 13 of Pat '748).
Claims 16-17 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 and 15-16 of U.S. Patent No. 11,699,736 in view of claims 16-17 and 20 of U.S. Patent No. 12,100,748.
Regarding claim 16, Pat '736 discloses the method of claim 15 as described above.
Pat '736 does not explicitly disclose at least one of the first protection layer, the second protection layer, or the third protection layer is an in-situ silane passivation layer.
Pat '748 teaches, in claim 16, at least one of the first protection layer, the second protection layer, or the third protection layer is an in-situ silane passivation layer (“at least one of the at least one protection layer or the third protection layer is an in-situ silane passivation layer ", in claim 16 of Pat '748, is interpreted as the same limitation), for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '736 to have the at least one of the first protection layer, the second protection layer, or the third protection layer being an in-situ silane passivation layer, as taught by Pat '748, for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Regarding claim 17, Pat '736 in view of Pat '748 discloses the method of claim 16 as described above.
Pat '748 further teaches, in claim 17, forming a second barrier layer after the forming a first barrier layer and before the forming a first work function metal layer (all limitations are the same with the limitations recited in claim 17 of Pat '748), for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Regarding claim 20, Pat '736 discloses the method of claim 14 as described above.
Pat '736 further discloses, in claim 16, forming the first dielectric layer over a second channel located over a different region of a substrate than the first channel (all limitations are the same with the limitations recited in claim 16 of Pat '736).
Pat '736 does not explicitly disclose removing one of the first and second protection layers from over the second channel while the first channel is exposed.
Pat '748 teaches, in claim 20, removing one of the first and second protection layers from over the second channel while the first channel is exposed (“removing one of the at least one protection layers from over the second semiconductor nanostructure while the first semiconductor nanostructure is exposed", in claim 20 of Pat '748, is interpreted as the same limitation), for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '736 to have the removing one of the first and second protection layers from over the second channel while the first channel is exposed, as taught by Pat '748, for the purpose of improving gate fill window, achieving lower gate resistance, and improving reliability for multiple Vt tuning with photolithographic patterning.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 and 15 of U.S. Patent No. 11,699,736 in view of Chang (US 2019/0148520).
Regarding claim 18, Pat '736 discloses the method of claim 14 as described above.
Pat '736 does not explicitly disclose the glue layer comprises a metal nitride selected from the group consisting of TiN, TaN, MoN, and WN.
Chang teaches, in at least figure 21A and related text, the method comprising the glue layer (2022, [64]) comprises a metal nitride selected from the group consisting of TiN, TaN, MoN, and WN, for the purpose of providing improved device performance and reliability ([13]).
Pat '736 and Chang are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '736 with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '736 to have the glue layer comprising a metal nitride selected from the group consisting of TiN, TaN, MoN, and WN, as taught by Chang, for the purpose of providing improved device performance and reliability ([13], Chang).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tsai (US 2013/0334690).
Regarding claim 14, Tsai discloses, in at least figures 7-8 and related text, a method, comprising:
forming a first dielectric layer (124, [18]) over a first channel (110 between 130, [19], figures);
forming a first work function metal layer (150, [20]) over the first dielectric layer (124, [18]);
forming a first protection layer (160, [21]) over the first work function metal layer (150, [20]);
forming a second protection layer (bottom layer of 170, [23]) over the first protection layer (160, [21]);
forming a glue layer (top layer of 170, [23]) over the second protection layer (bottom layer of 170, [23]); and
forming a first metal layer (190, [24]) over the glue layer (middle layer of 170, [23]).
Regarding claim 15, Tsai discloses the method of claim 14 as described above.
Tsai further discloses, in at least figures 7-8 and related text, forming a third protection layer (middle layer of 170, [23]) over the first protection layer (160, [21]) and the second protection layer (bottom layer of 170, [23]) before forming the first metal layer (190, [24]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2013/0334690) in view of Chang (US 2019/0148520).
Regarding claim 18, Tsai discloses the method of claim 14 as described above.
Tsai does not explicitly disclose the glue layer comprises a metal nitride selected from the group consisting of TiN, TaN, MoN, and WN.
Chang teaches, in at least figure 21A and related text, the method comprising the glue layer (2022, [64]) comprises a metal nitride selected from the group consisting of TiN, TaN, MoN, and WN, for the purpose of providing improved device performance and reliability ([13]).
Tsai and Chang are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tsai with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Tsai to have the glue layer comprising a metal nitride selected from the group consisting of TiN, TaN, MoN, and WN, as taught by Chang, for the purpose of providing improved device performance and reliability ([13], Chang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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