Prosecution Insights
Last updated: October 22, 2026
Application No. 18/789,349

SEMICONDUCTOR DEVICE AND METHOD

Non-Final OA §102§Other
Filed
Jul 30, 2024
Priority
Aug 16, 2018 — continuation of 10/510,871 +3 more
Examiner
HARRISTON, WILLIAM A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
970 granted / 1083 resolved
+21.6% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
19 currently pending
Career history
1111
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
45.7%
+5.7% vs TC avg
§102
33.7%
-6.3% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1083 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed on 07/30/2024 has been considered. Drawings The drawings filed on 07/30/20245 are acceptable. Specification The abstract of the disclosure and the specification filed on 07/30/2024 are acceptable. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Duan (US 2005/0181587). Regarding claim 1, Duan (figures 3B and 4B) discloses: A semiconductor device comprising: a first material (100, ¶0131) extending from a first side of a first gate electrode (204, ¶0131) to a second side of the first gate electrode; a first semiconductor sheath (302, ¶0139) around the first material (100, ¶0137), the first semiconductor sheath having a thickness that is less than 2 nanometers (¶0139 teaches thickness can be a single monolayer). a second material (100) extending from a first side of a second gate electrode (204) to a second side of the second gate electrode and a second semiconductor sheath (302) around the second material, the second semiconductor sheath having a thickness less than 2 nanometer (¶0139), wherein the second semiconductor sheath (¶00139) comprises atoms of the first material and the second material (sheath 302 is a doped outer shell of the underlying semiconductor core)” Regarding claim 2, Duan further discloses: wherein the first semiconductor sheath has a thickness that is less than 1 nm (¶0139). Regarding claim 3, Duan further discloses: wherein the first semiconductor sheath has a thickness that is less than 0.96 nm (¶0139). Regarding claim 4, Duan further discloses: wherein the first material has a first diameter of between about 2 nm and about 20 nm (¶0314). Regarding claim 5, Duan further discloses: wherein the first material has a first diameter of between about 2 nm and about 8 nm (¶0314). Allowable Subject Matter Claims 6 and 7 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 6, the prior art does not disclose “wherein the first semiconductor sheath has a graded percentage concentration of germanium” in combination with the remaining claimed features. Claim 8-20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 8, the prior art does not disclose “a second semiconductor sheath extending through a second gate dielectric, the second semiconductor sheath comprising the first material and the second material, the second semiconductor sheath being no larger than 2 nm; a third semiconductor located on a first side of the second semiconductor sheath, the third semiconductor comprising the second material; and a fourth semiconductor located on a second side of the second semiconductor sheath, the fourth semiconductor comprising the first material, the second side of the second semiconductor sheath being located within the second semiconductor sheath” in combination with the remaining claimed features. Regarding claim 15, the prior art does not disclose “a second level of semiconductor material different from the first level of semiconductor material, the second level comprising the first semiconductor material, the second semiconductor material, and a second sheath comprising material from both the first semiconductor material and the second semiconductor material, the second semiconductor material being surrounded by the second sheath” in combination with the remaining claimed features. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Jul 30, 2024
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102, §Other (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.4%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1083 resolved cases by this examiner. Grant probability derived from career allowance rate.

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