Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made the instant application is a divisional of US Patent application 17693204 and the US Patent application 17693204 has a provisional application 63225101 filed on 07/23/2021.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 12 recites:
“forming an epitaxial semiconductor layer on the substrate”. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 depends from claim 12.
Claim 14 recites:
“forming a plurality of stacked second semiconductor nanostructures over the substrate”. There is insufficient antecedent basis for this limitation in the claim.
Claims 15-16 depend from claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 6-8, 11, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US 20190067125 A1 – hereinafter Chiang).
Regarding Claim 1, Chiang teaches a method (see the entire document; Fig. 1; specifically, ([0040] - [0044]), and as cited below), comprising:
forming a plurality of stacked first channels (25 of transistor Q1 – Fig. 1 – [0040]-[0042]) of a first transistor (Q1 – [0040]) over a substrate (10);
forming a first source/drain region (40 – [0044]) of the first transistor (Q1) in contact with each of the first channels (25 of Q1); and
forming a plurality of stacked second channels (25 of transistor Q2); and
forming a second source/drain region (40 of Q2) in contact with a highest second channel (40 of Q2 is in contact with top 25 of Q2 as shown in Fig. 1) of the stacked second channels (25 of transistor Q2) and having a bottom surface that is higher than a lowest second channel of the stacked second channels (Fig. 1 shows bottom surface of 40 of Q2 is higher than the lowest 25 of Q2).
Regarding Claim 6, Chiang teaches the method of claim 1, wherein a lowest second channel is non-functioning nanostructure (Fig. 1 shows that dielectric layer 35 electrically separated 40 from the lowest 25 of transistor Q2. Therefore, lowest 25 does not contribute to forming transistor Q2).
Regarding Claim 7, Chiang teaches the method of claim 1, comprising forming a first gate metal (left 58 – [0042]) surrounding each of the first channels 25; and forming a second gate metal (right 58) surrounding each of the second channels (right 25).
Regarding Claim 8, Chiang teaches the method of claim 1, wherein there is same number of first channels and second channels (Fig. 1 shows same number of 25 for Q1 and Q2).
Regarding Claim 11, Chiang teaches a method (see the entire document; Fig. 1; specifically, ([0040] - [0044]), and as cited below), comprising:
forming a plurality of stacked first semiconductor nanostructures of a first transistor (25 of transistor Q2 – Fig. 1 – [0040]-[0042]);
forming a first gate metal (58 of Q2 – [0042]) surrounding each of the first semiconductor nanostructures (25); and
forming a first source/drain region (40 of Q2 – [0044]) in contact with a highest first semiconductor nanostructure of the plurality of first semiconductor nanostructures (top 25 of Q2) and electrically isolated from a lowest first semiconductor nanostructure of the plurality of first semiconductor nanostructures (that is, 40 of Q2 is isolated from bottom 25 by dielectric layer 35 – [0044]).
Regarding Claim 14, Chiang teaches the method of claim 11, comprising: forming a plurality of stacked second semiconductor nanostructures (25 of transistor Q1 – Fig. 1 – [0040]-[0042]) over the substrate (10) and corresponding to channel regions of a second transistor (Q1); and forming a second source/drain region (40) in contact with each of the second semiconductor nanostructures (25).
Allowable Subject Matter
Claims 2-5, 9-10, 12-13, 15-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The method of claim 1, comprising forming a first epitaxial semiconductor layer extending from the substrate; below the first source/drain region and forming a first dielectric isolation structure on the first semiconductor layer, forming the first source/drain region on the first dielectric isolation structure, the first dielectric isolation structure is between the epitaxial semiconductor layer and the first source/drain region, the first epitaxial layer having a top surface that is lower than a lowest first channel of the stacked first channels; forming a second epitaxial semiconductor layer on the substrate; forming a second dielectric isolation structure on the second epitaxial semiconductor layer; and forming the second source/drain region on the second dielectric isolation structure, the second dielectric isolation structure being between the second epitaxial semiconductor layer and the second source/drain region and in contact with the lowest second semiconductor nanostructure.
Claim 3 depends from claim 2.
Regarding claim 4:The method of claim 1, comprising: forming a first epitaxial semiconductor layer having a top surface that is lower than a lowest first channel of the stacked first channel; forming the first source/drain region on the first epitaxial semiconductor layer; forming a second epitaxial semiconductor layer extending upward from the substrate in contact with the lowest second channel of the plurality of stacked second channels; forming a dielectric isolation structure on the second epitaxial semiconductor layer; and forming the second source/drain region on the dielectric isolation structure, the dielectric isolation structure being between the second epitaxial semiconductor layer and the second source/drain region.
Claim 5 depends from claim 4.
Regarding claim 9: The method of claim 1, comprising: forming a gate metal surrounding each of the second channels; forming a plurality of dielectric inner spacer structures each positioned adjacent to the gate metal between a respective pair of second channels; forming an epitaxial semiconductor layer extending from the substrate below the second source/drain region and in contact with the lowest second semiconductor nanostructure; and forming a dielectric isolation structure between the second epitaxial semiconductor layer and the second source/drain region and in contact with at least one of the dielectric inner spacer structures.
Claim 10 depends from claim 9.
Regarding claim 12: The method of claim 11, comprising: forming an epitaxial semiconductor layer on the substrate and in contact with the bottom first semiconductor nanostructure; and forming the first source/drain region on the epitaxial semiconductor layer.
Claim 13 depends from claim 12.
Regarding claim 15: The method of claim 14, wherein a bottom surface of the second source/drain region is lower than a bottom surface of the first source/drain region.
Claim 16 depnds from claim 15.
REASON FOR ALLOWANCE
Claims 17-20 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 17, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20190067125 A1 to Chiang) substantially teach(es) some of limitations in claim 17 as indicated in the rejections of claim 1, but not the limitations of “growing an epitaxial semiconductor layer over the substrate and in contact with a bottom first semiconductor nanostructure of the plurality of first semiconductor nanostructures……forming a second source/drain region of the second transistor in contact with all of the second semiconductor nanostructures and having a bottom surface that is lower than the bottom surface of the first source/drain region” as recited in claim 1. Therefore, claim 1 is deemed patentable over the prior art.
Regarding claims 18-20, they are allowed due to their dependencies on claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
Prosecution Insights