DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the current path is formed from the first conductive segment through the conductive via, the second conductive segment, and the third conductive segment to the active area, as required by claim 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
As shown in Figs. 4 and 6 and as described in ¶ [0048] of the specifications, the current path is formed from the first conductive line (111) through the conductive via (121), the first conductive segment (131), the second conductive segment (141), and the third conductive segment (132) to the active area (161).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the underlined subject matter is required:
a. claim 4 requires a height of the active area and a height of the first conductive segment, such that said heights are substantially equal to each other;
b. claim 5 requires an isolation segment that is aligned with the second conductive segment along a vertical direction;
c. claim 7 requires a width of the active area that is greater than a width of the second conductive segment;
d. claim 12 requires a width of the first conductive line that is smaller than the first conductive segment;
e. claim 13 requires a first direction that the gate extends and a second direction along which a second conductive line passes the gate;
f. claim 15 requires a height of the second conductive area being substantially equal to a height of the first conductive segment;
g. claim 16 requires a current path is formed from the first conductive segment through the conductive via, the second conductive segment, and the third conductive segment to the active area (also see Drawings Objection above);
g. claim 17 requires a width of the gate being smaller than a width of the second conductive segment;
h. claim 18 requires a width of the conductive line is greater than the first conductive segment;
i. claim 19 requires the conductive line and the second conductive segment are parallel to each other; and
j. claim 20 requires the conductive line and the second conductive segment overlap each other from a top view.
Claim Objections
Claim 14 is objected to because of the following informalities: typographical error in the limitation: wherein a top surface of the third conducive [sic: conductive] segment (see line 9). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation of “a width of the first conductive line is smaller than the first conductive segment.” It is not clear what attribute of the first conductive segment is compared to the width of the conductive line. For the purpose of compact prosecution, the examiner will cite art that teaches the width of the first conductive line that is smaller than a width of the first conductive segment.
Claim 18 and by extension, dependent claims 19-20, recites the limitation of “wherein a width of the conductive line is greater than the first conductive segment.” It is not clear what attribute of the first conductive segment is compared to the width of the conductive line. For the purpose of compact prosecution, the examiner will cite art that teaches the width of the first conductive line that is greater than a width of the first conductive segment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 14 and 18-20 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Lim (US 2017/0133365 A1).
Regarding claim 1, Lim teaches a method (Fig. 14), comprising:
forming an active area (430m);
forming a first conductive segment (1320) and a second conductive segment (1342) that is above the active area;
forming a third conductive segment (1310&1325) contacting the first conductive segment and contacting the second conductive segment; and
forming a first conductive via (1350 is vertically higher than 1320) above the first conductive segment;
wherein the active area is electrically coupled to the first via through the second conductive segment, the third conductive segment, and the first conductive segment (Fig. 14 shows 1342, 1310&1325, and 1320, as a unit, connects 430m to 1350).
Regarding claim 5, the method of claim1, further comprising: forming an isolation segment (Fig. 1 and ¶ [0024]: insulating layers separating each interconnect metal layers M1-M9) that is above the second conductive segment (Fig. 14 shows M1 above 1342) and aligned with the second conductive segment along a vertical direction (vertical direction in Fig. 14; Fig. 14 shows 1342 vertically aligned with M1; Fig. 1 shows various layers M1-M9 vertically aligned, with ¶ [0024] disclosing insulating layers between each metal layer ).
Regarding claim 14, Lim teaches a method (see Fig. 14) comprising:
forming a first conductive segment (1320), a second conductive segment (1342 & 1310), and a third conductive segment (1325), wherein the second conductive segment is between the first conductive segment and the third conductive segment (see Fig. 14),
wherein a height (height of 1342 & 1310 as a unit) of the second conductive segment is different from a height (height of 1325) of the third conductive segment; and
forming a conductive via (1350 is vertically higher than 1320) above the first conductive segment, wherein a top surface (top surface of 1325) of the third conducive segment is aligned (all three surfaces are coplanar) with a top surface (top surface of 1310) of the second conductive segment and a bottom surface (bottom surface of 1350) of the conductive via.
Regarding claim 18, the method of claim 14, further comprising: forming a conductive line (M1; Fig. 14) that is above and coupled to the conductive via, wherein a width (horizontal width of M1) of the conductive line is greater than the first conductive segment (horizontal width of 1320; see 112b rejection above).
Regarding claim 19, the method of claim 18, wherein the conductive line and the second conductive segment are parallel to each other (Fig. 14 shows M1 and 1310 are parallel to each other).
Regarding claim 20, the method of claim 18, wherein the conductive line (M1 in Fig. 14 is labelled 412 in Fig. 13A) and the second conductive segment (1310) overlap with each other from a top view (Fig. 13A is a top view of Fig. 14).
Claims 8-11 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Rashed ‘607 (US 8,618,607 B1).
Regarding claim 8, Rashed ‘607 teaches a method (Fig. 5D), comprising:
forming a gate (150PG; see Col. 9, Ln. 4);
forming a first conductive segment (left 190P), a second conductive segment (192P) , and a third conductive segment (right 190P), wherein the first conductive segment and the third conductive segment are arranged on opposite sides (left and right sides of 192P) of the second conductive segment and the second conductive segment is connected to the gate (Fig. 5D shows 192P connected to 150PG);
forming a conductive via (194P) on the first conductive segment, wherein the second conductive segment contacts the conductive via (Fig. 5D shows 194P on left 190P and contacting 192P); and
forming a first conductive line (140H) electrically coupled to the first conductive segment and the second conductive segment through the conductive via (Fig. 5D shows 140H coupled to left 190P and 192P through 194P).
Regarding claim 9, the method of claim 8, wherein the first conductive line is above the first conductive segment and the conductive via (Fig. 5D shows 140H above left 190P and 194P).
Regarding claim 10, the method of claim 8, wherein a current path is formed from the first conductive line through the conductive via, the first conductive segment, and the second conductive segment to the third conductive segment (since all conductive segments are electrically connected, then an artisan would recognize that there is a current flowing through them).
Regarding claim 11, the method of claim 8, wherein the gate is below the second conductive segment (Fig. 5D shows 150PG below 192P) and interposed between the first conductive segment and the third conductive segment (Fig. 5D shows 150PG in between left and right 190P).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 6-7, 14-16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rashed ‘982 (US 2013/0146982 A1) in view of Lim (US 2017/0133365 A1).
Regarding claim 1, Rashed ‘982 teaches a method (Fig. 1), comprising:
forming an active area (28);
forming a first conductive segment (36) and a second conductive segment (34 & 37) that is above the active area;
forming a first conductive via (38) above the first conductive segment;
However, Rashed ‘982 does not teach: forming a third conductive segment contacting the first conductive segment and contacting the second conductive segment; wherein the active area is electrically coupled to the first via through the second conductive segment , the third conductive segment, and the first conductive segment.
Lim, in the same field of invention, teaches a method (Fig. 14) comprising:
forming a third conductive segment (1310) contacting the first conductive segment (1320) and contacting the second conductive segment (1342);
wherein the active area (430m) is electrically coupled to the first via (1350) through the second conductive segment, the third conductive segment, and the first conductive segment (Fig. 14 shows 1342, 1310, and 1320, as a unit, connects 430m to 1350).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lim into the method of Rashed ‘982 to form a third conductive segment contacting the first conductive segment and contacting the second conductive segment, wherein the active area is electrically coupled to the first via through the second conductive segment, the third conductive segment, and the first conductive segment. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of tying sources and gates of transistors (see Lim Fig. 12) to form an electrical barrier (¶ [0020]) that provide a desired electrical isolation in certain nodes (¶ [0054]-[0055]), for the further purpose of improving the performance and scalability of the device (¶ [0004] ).
Regarding claim 2, the method of claim 1, further comprising: forming a gate (30; Rashed ‘982 Fig. 1) underneath the third conductive segment (in view of Lim, 30 is under the third conductive segment), wherein a height of the gate (height of 30) plus a height (height of 1310 in Lim Fig. 14) of the third conductive segment is substantially equal (Rashed ‘982 ¶ [0021]: other heights of gates may be realized; ¶ [0028]: other heights of conductive elements may be realized) to a height (height of 34 & 37) of the second conductive segment.
Regarding claim 4, the method of claim 1, wherein a height of the active area (height of 28; Rashed ‘982 Fig. 1) plus a height (height of 34 & 37) of the second conductive segment is substantially equal (Rashed ‘982 ¶ [0021]: other heights of gates may be realized; ¶ [0028]: other heights of conductive elements may be realized) to a height of the first conductive segment (36).
Regarding claim 6, the method of claim 1, wherein a height (height of 36) of the first conductive segment is greater (Rashed ‘982 ¶ [0021]: other heights of gates may be realized; ¶ [0028]: other heights of conductive elements may be realized) than a height (height of 34 & 37) of the second conductive segment.
Regarding claim 7, the method of claim 1, further comprising: forming a gate (30; Rashed ‘982 Fig. 1) underneath the third conductive segment (in view of Lim, 30 is under the third conductive segment), wherein a width (vertical height of 28 can be considered a width since this is a 3D object) of the active area is greater (Rashed ‘982 ¶ [0021]: other heights of gates may be realized; ¶ [0028]: other heights of conductive elements may be realized) than a width (vertical height of 34 & 37 can be considered a width) of the second conductive segment plus a width (height of 30) of the gate.
Regarding claim 14, Rashed ‘982 teaches a method comprising:
forming a first conductive segment (36), a second conductive segment (34 & 37), and
forming a conductive via (38) above the first conductive segment.
However, Rashed ‘982 does not teach a third conductive segment, wherein the second conductive segment is between the first conductive segment and the third conductive segment, wherein a height of the second conductive segment is different from a height of the third conductive segment; and wherein a top surface of the third conducive segment is aligned with a top surface of the second conductive segment and a bottom surface of the conductive via.
Lim, in the same field of invention, teaches a method (Fig. 14) comprising:
a third conductive segment (1310 & 1325), wherein the second conductive segment (1342) is between the first conductive segment (1320) and the third conductive segment,
wherein a height (vertical height of 1342) of the second conductive segment is different from a height (vertical height of 1310 & 1325) of the third conductive segment; and
wherein a top surface (top surface of 1310) of the third conducive segment is aligned (said surfaces are aligned along the horizontal axis to provide appropriate contact that results in desired electrical coupling) with a top surface (top surface of 1342) of the second conductive segment and a bottom surface (bottom surface of 1350) of the conductive via (1350).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lim into the device of Rashed ‘982 to add a third conductive segment, wherein the second conductive segment is between the first conductive segment and the third conductive segment, wherein a height of the second conductive segment is different from a height of the third conductive segment; and wherein a top surface of the third conducive segment is aligned with a top surface of the second conductive segment and a bottom surface of the conductive via. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of tying sources and gates of transistors (see Lim Fig. 12) to form an electrical barrier (¶ [0020]) that provide a desired electrical isolation in certain nodes (¶ [0054]-[0055] ), for the further purpose of improving the performance and scalability of the device (¶ [0004] ).
Regarding claim 15, method of claim 14, further comprising:
forming an active area (28; Rashed ‘982 Fig. 1) and a gate (30) that is disposed above the active area (top portions of gate 30 is above 28),
wherein a sum of a height of the active area (height of 28), a height of the gate (height of 30), and a height of the second conductive segment (height of 34 & 37) is substantially equal (Rashed ‘982 ¶ [0020]: other heights of drain 28 may be realized; also drains may not be raised above substrate 22, which is the same teaching in Lim Fig. 14; ¶ [0021]: other heights of gates may be realized; ¶ [0028]: other heights of conductive elements may be realized) to a height (height of 36) of the first conductive segment.
Regarding claim 16, the method of claim 15, wherein a current path is formed from the first conductive segment through the conductive via, the second conductive segment, and the third conductive segment to the active area (since all conductive segments are electrically connected, then an artisan would recognize that there is a current flowing through them).
Regarding claim 17, the method of claim 15, wherein a width (width of 420d; see Lim Fig. 14) of the gate is smaller than a width (width of 1310) of the second conductive segment.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Rashed ‘982 (US 2013/0146982 A1) in view of Lim (US 2017/0133365 A1) as applied to claim 2 above, and further in view of Rashed ‘607 (US 8,618,607 B1).
Regarding claim 3, Rashed ‘982 et al. teaches the method of claim 2, but do not teach: wherein the gate is between the first conductive segment and the second conductive segment.
Rashed ‘607, in the same field of invention, teaches a method (Figs. 5A-5E) wherein the gate (150PG) is between the first conductive segment (left 175& left 190) and the second conductive segment (right 175 & right 190).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Rashed ‘607 into the device of Rashed ‘982 et al. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing various PFET / NFET devices that would require multiple sources (S; see Fig. 5A-5E) of various transistors (leftmost and rightmost gates) to be situated with a gate (150PG/150NG) in between them, with the gate acting as an isolating electrode (see Fig. 3 and Col, 5 , Ln. 20-21) used to improve the issues related to shorting in applications such as NAND circuits (Col. 1. Ln 18 through Col. 2, Ln 3).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Rashed ‘607 (US 8,618,607 B1) as applied to claim 8 above, and further in view of Yamada (US 2012/0211898 A1).
Regarding claim 12, Rashed ‘607 teaches the method of claim 8, but does not teach: wherein a width of the first conductive line is smaller than the first conductive segment.
Yamada, in the same field of invention, teaches a method (Fig. 3) wherein a width (Dsi) of the first conductive line (13) is smaller than the first conductive segment (11 has a width of Dh; see also 35 USC 112(b) rejection above).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamada into the method of Rashed ‘607 to make the width of the first conductive line smaller compared to the width of the first conductive segment. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of increasing the device reliability and yield by reducing SM defect (Yamada ¶ [0039]-[0041] ).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Rashed ‘607 (US 8,618,607 B1) as applied to claim 8 above, and further in view of Lee (US 2016/0268243 A1).
Regarding claim 13, Rashed ‘607 teaches method of claim 8, wherein the gate (150PG) extends in a first direction (vertical direction; Fig. 5A). However, Rashed ‘607 does not teach: wherein the method further comprises: forming a second conductive line passing the gate along a second direction different from the first direction.
Lee, in the same field of invention, teaches a method comprising: forming a second conductive line (138; Fig. 3A) passing the gate (124) along a second direction (horizontal direction) different from the first direction (gate 124 extends vertically).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee into the method of Rashed ‘607 to add a second conductive line that passes through the gate in a perpendicular direction. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using the second conductive line to connect other transistors (MP6; Lee ¶ [0052] ) to an input terminal of yet another transistor (MN8), for the further purpose of reducing the footprint of the layout of the device (¶ [0057] ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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