Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,142,529 B2 in view of Yu et al.
In addition, patents US 11,776,852 B2; US 11,037,828 B2 to Yu et al. are considered as being linked to this Double Patenting Rejection.
Although the claims at issue are not identical, they are not patentably distinct from each other because the patent renders obvious the instant application.
Regarding independent claim 1: Yu teaches (e.g., Claims 1-7) a semiconductor device comprising:
a plurality of spaced apart nanowires stacked over a substrate;
a gate electrode wrapping around each nanowire of the plurality of nanowires; and
source/drain regions disposed over the substrate on opposing sides of the gate electrode,
wherein each of the nanowires includes an inner layer having a first Ge concentration, and two opposing outer layers having a second Ge concentration, wherein the second Ge concentration is greater than the first Ge concentration, and each nanowire extends through the source/drain regions (Claim 1).
Regarding claim 2: Yu teaches the claim limitation if the semiconductor device of claim 1, on which this claim depends,
wherein the first Ge concentration is more than 10 atomic % and less than 50 atomic % and the second Ge concentration is more than 30 atomic % and less than 90 atomic % (Claim 2).
Regarding claim 3: Yu teaches the claim limitation if the semiconductor device of claim 1, on which this claim depends,
wherein a thickness of the inner layer is 3 nm to 15 nm (Claim 3).
Regarding claim 4: Yu teaches the claim limitation if the semiconductor device of claim 3, on which this claim depends,
wherein a thickness of each of the outer layers is 0.5 nm to 2 nm (Claim 4).
Regarding claim 5: Yu teaches the claim limitation if the semiconductor device of claim 1, on which this claim depends,
further comprising a high-k dielectric layer disposed between the gate electrode and the nanowires (Claim 7).
Regarding claim 6: Yu teaches the claim limitation if the semiconductor device of claim 1, on which this claim depends,
wherein the gate electrode is made of a metal (Claim 1).
Regarding claim 7: Yu teaches the claim limitation if the semiconductor device of claim 1, on which this claim depends,
wherein each of the nanowires further includes Si (Claim 1).
Regarding independent claim 8: Yu teaches (e.g., Claims 1-7) a semiconductor device comprising:
a plurality of spaced apart nanowires stacked over a substrate;
a gate electrode wrapping around each nanowire of the plurality of nanowires; and
source/drain regions disposed over the substrate on opposing sides of the gate electrode,
wherein each nanowire includes an inner layer and two opposing outer layers, wherein a thickness of the inner layer is greater than a thickness of either of the outer layers,
the inner layer and the outer layers are made of different materials, and
each nanowire extends through the source/drain regions (Claim 1).
Regarding claim 9: Yu teaches the claim limitation if the semiconductor device of claim 8, on which this claim depends,
wherein the inner layer and the outer layers include Ge, and a first Ge concentration in the inner layer is different than a second Ge concentration in outer layers (Claim 2).
Regarding claim 10: Yu teaches the claim limitation if the semiconductor device of claim 9, on which this claim depends,
wherein the first Ge concentration is more than 10 atomic % and less than 50 atomic % and the second Ge concentration is more than 30 atomic % and less than 90 atomic % (Claim 2).
Regarding claim 11: Yu teaches the claim limitation if the semiconductor device of claim 8, on which this claim depends,
wherein a thickness of the inner layer is 3 nm to 15 nm (Claim 3).
Regarding claim 12: Yu teaches the claim limitation if the semiconductor device of claim 8, on which this claim depends,
wherein a thickness of each of the outer layers is 0.5 nm to 2 nm (Claim 4).
Regarding claim 13: Yu teaches the claim limitation if the semiconductor device of claim 8, on which this claim depends,
further comprising a high-k dielectric layer disposed between the gate electrode and the nanowires (Claim 7).
Regarding claim 14: Yu teaches the claim limitation if the semiconductor device of claim 8, on which this claim depends,
wherein each of the nanowires further includes Si (Claim 1).
Regarding independent claim 15: Yu teaches (e.g., Claims 15-20) a semiconductor device, comprising:
a plurality of spaced apart semiconductor layers stacked over a substrate a first direction, the first direction extending substantially perpendicular to a main surface of the substrate; and
a gate electrode layer wrapping around the semiconductor layers,
wherein each of the semiconductor layers include an inner layer comprising having a first Ge concentration, and two opposing outer layers having a second Ge concentration,
wherein the first and second Ge concentrations are different, and
a thickness of each inner layer along the first direction is greater than a distance between adjacent semiconductor layers along the first direction (Claim 15).
Regarding claim 16: Yu teaches the claim limitation if the semiconductor device of claim 15, on which this claim depends,
wherein the first Ge concentration is more than 10 atomic % and less than 50 atomic % and the second Ge concentration is more than 30atomic % and less than 90 atomic % (Claim 16).
Regarding claim 17: Yu teaches the claim limitation if the semiconductor device of claim 15, on which this claim depends,
wherein a thickness of the inner layer is 3 nm to 15 nm (Claim 17).
Regarding claim 18: Yu teaches the claim limitation of the semiconductor device of claim 15, on which this claim depends,
wherein a thickness of each of the outer layers is 0.5 nm to 2 nm (Claim 18).
Regarding independent claim 15: Yu teaches (e.g., Claims 8-14) a semiconductor device, comprising:
a plurality of spaced apart semiconductor layers stacked over a substrate a first direction, the first direction extending substantially perpendicular to a main surface of the substrate; and
a gate electrode layer wrapping around the semiconductor layers,
wherein each of the semiconductor layers include an inner layer comprising having a first Ge concentration, and two opposing outer layers having a second Ge concentration,
wherein the first and second Ge concentrations are different, and
a thickness of each inner layer along the first direction is greater than a distance between adjacent semiconductor layers along the first direction (Claim 8).
Regarding claim 19: Yu teaches the claim limitation of the semiconductor device of claim 15, on which this claim depends,
further comprising a high-k dielectric layer disposed between the gate electrode and the semiconductor layers (Claim 14).
Regarding claim 20: Yu teaches the claim limitation of the semiconductor device of claim 15, on which this claim depends,
wherein each of the semiconductor layers further includes Si (Claim 9).
Allowable Subject Matter
Claims 1-20 would be allowable if all rejections above are overcome.
Regarding claim 1: allowable subject matter:
“wherein each of the nanowires includes an inner layer having a first Ge concentration, and two opposing outer layers having a second Ge concentration, wherein the second Ge concentration is greater than the first Ge concentration, and each nanowire extends through the source/drain regions”.
Regarding claim 8: allowable subject matter:
“wherein each nanowire includes an inner layer and two opposing outer layers, wherein a thickness of the inner layer is greater than a thickness of either of the outer layers, the inner layer and the outer layers are made of different materials, and each nanowire extends through the source/drain regions”.
Regarding claim 15: allowable subject matter:
“wherein each of the semiconductor layers include an inner layer comprising having a first Ge concentration, and two opposing outer layers having a second Ge concentration, wherein the first and second Ge concentrations are different, and a thickness of each inner layer along the first direction is greater than a distance between adjacent semiconductor layers along the first direction. 16. The semiconductor device of claim 15, wherein the first Ge concentration is more than 10 atomic% and less than 50 atomic% and the second Ge concentration is more than 30 atomic% and less than 90 atomic%”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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