Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 07/30/2024. Currently, claims 1-20 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Pub. No. US 2016/0043035 A1, herein Lin) in view of Sun et al. (U.S. Pat. No. 4,926,237, herein Sun).
Regarding claim 1, Lin discloses a semiconductor structure, comprising: a source/drain epitaxial layer 58 in a substrate 20 ([0020]); a metal silicide layer 30 on the source/drain epitaxial layer ([0016]); and a metal contact between two gate electrodes 54 ([0020]), wherein the metal contact comprises: a first metal layer 26 ([0014]) in contact with the source/drain epitaxial layer and the metal silicide layer; a barrier layer 28 ([0015]) in contact with the first metal layer; a second metal layer 34 ([0018]); and a third metal layer 70 ([0020]) in contact with the second metal layer (Fig. 7).
Lin does not specifically show a liner layer in contact with the barrier layer, wherein a second contact metal layer is in contact with the liner layer.
However, in the same field of endeavor, Sun discloses a semiconductor structure, comprising: a source/drain layer 14 in a substrate 12 (column 3 lines 3-6); a metal silicide layer 25 on the source/drain epitaxial layer (column 3 line 40-45); and a metal contact, wherein the metal contact comprises: a first metal layer 22 in contact with the source/drain epitaxial layer and the metal silicide layer; a barrier layer 26 in contact with the first metal layer (column 3 lines 40-45); a liner layer 24 in contact with the barrier layer (column 3 lines 29-32); a second metal layer 28 in contact with the liner layer (column 4 lines 34-36); and a third metal layer 32 in contact with the second metal layer (column 4 lines 65-67) to provide an improved device metallization (column 1 lines 6-11 and column 2 lines 7-10).
Therefore, given the teachings of Sun, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin in view of Sun by employing the liner layer.
Regarding claim 2, Lin in view of Sun teaches the semiconductor structure of claim 1, wherein: the first metal layer, the metal silicide layer, and the barrier layer comprise a first metal material; and the liner layer, the second metal layer, and the third metal layer comprise a second metal material different from the first metal material (Lin: [0014]-[0016] and Sun: column 3 lines 3-45).
Regarding claim 3, Lin in view of Sun shows the height of the metal contact being larger than the width of the metal contact but does not specifically state the claimed ratio of between about 3 and about 10. However, the claimed ratio is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed ratio because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another ratio. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 4, Lin in view of Sun teaches the semiconductor structure of claim 1, wherein: the first metal layer comprises titanium (Ti); and the third metal layer comprises cobalt (Co) (Lin: [0014], [0022] and Sun: column 3 lines 23-39, column 5 lines 27-32). See In re Leshin, 277 F.2d 197, 199 (CCPA 1960); the selection of a known material based upon its suitability for the intended use is a design consideration within the skill of the art.
Claims 1, 6-7 and 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Pub. No. US 2015/0235956 A1, herein Lin-56) in view of Adusumilli et al. (Pub. No. US 2017/0117225 A1, herein Adusumilli).
Regarding claim 1, Lin-56 discloses a semiconductor structure, comprising: a source/drain epitaxial layer 220 in a substrate 202; a metal silicide layer 218 on the source/drain epitaxial layer ([0014]); and a metal contact, wherein the metal contact comprises: a first metal layer 208 in contact with the source/drain epitaxial layer and the metal silicide layer ([0014]); a second metal layer 212 ([0014]); and a third metal layer 216 in contact with the second metal layer ([0017]).
Lin-56 does not specifically show a metal contact between two gate electrodes, wherein the metal contact comprises: a barrier layer in contact with the first metal layer; a liner layer in contact with the barrier layer; a second metal layer in contact with the liner layer.
However, in the same field of endeavor, Adusumilli discloses a semiconductor structure, comprising: a source/drain layer 12/13 in a substrate 7-8; and a metal contact between two gates 11 ([0023]-[0024]), wherein the metal contact comprises: a first metal layer 45 in contact with the source/drain epitaxial layer and the metal silicide layer ([0050]); a barrier layer 30 in contact with the first metal layer ([0041]); a liner layer 35 in contact with the barrier layer ([0041]); a second metal layer 28 in contact with the liner layer ([0041]) to provide low resistance contact structures for middle of the line (MOL) trench contacts ([0018]).
Therefore, given the teachings of Adusumilli, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin-56 in view of Adusumilli by employing the liner layer and barrier layer.
Regarding claim 6, Lin-56 in view of Adusumilli teaches the semiconductor structure of claim 1, wherein top surfaces of the second and third metal layers are coplanar (Lin-56: Fig. 8 & [0018], and Adusumilli: Fig. 6 & [0049]).
Regarding claims 7, 10, 12, 14 and 17, the applicant is referred to the rejection applied to claims 1 and 6.
Regarding claim 11, Lin-56 in view of Adusumilli teaches the semiconductor structure of claim 10, wherein a width of an upper portion of the third metal layer is greater than a width of a lower portion of the third metal layer (Lin-56: Fig. 8 & [0018], and Adusumilli: Fig. 6 & [0049]).
Regarding claim 13, Lin-56 in view of Adusumilli teaches the semiconductor structure of claim 7, wherein the first and second gate structures comprise first and second capping layers (dielectric layer 15 in Adusumilli), respectively, and wherein the first metal layer is between the first and second capping layers (Lin-56: Fig. 8 & [0018], and Adusumilli: Fig. 6 & [0049]).
Regarding claim 15, Lin-56 in view of Adusumilli teaches the semiconductor structure of claim 14, wherein the gate structure comprises: a high-k dielectric layer (dielectric 8 of Adusumilli, [0022], Having a high-k gate dielectric layer such as hafnium oxide as an alternative for silicon oxide is well-known in the art. ) on the substrate; a gate electrode (gate electrode 11 of Adusumilli) on the high-k dielectric layer; and a gate spacer (gate spacers 14 of Adusumilli) on the substrate and adjacent to the gate electrode (Adusumilli: Fig. 6 & [0049]).
Regarding claim 16, Lin-56 in view of Adusumilli teaches the semiconductor structure of claim 15, further comprising a dielectric layer (dielectric layer 15 in Adusumilli) between the gate spacer and the first metal layer (Lin-56: Fig. 8 & [0018], and Adusumilli: Fig. 6 & [0049]).
Regarding claim 18, Lin-56 in view of Adusumilli shows the height of the metal contact being larger than the width of the metal contact but does not specifically state the claimed ratio of between about 3 and about 10. However, the claimed ratio is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed ratio because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another ratio. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 19, Lin-56 in view of Adusumilli teaches the semiconductor structure of claim 14, wherein the S/D contact structure further comprises a silicide layer between the barrier layer and the S/D region (Lin-56: Fig. 8 & [0014]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Sun, as applied above, and further in view of Mcfeely et al. (Pat. No. 9,048,296 B2)
Regarding claim 5, Sun shows a wavy bottom for the third metal layer 32 but does not specifically state the third metal layer comprises a curved bottom surface.
However, in the same field of endeavor, Mcfeely shows a metal contact comprising conductive layers 202b, 302 and 402, and a barrier layer 202a, wherein the third metal layer comprises a curved bottom surface (Fig. 4).
Therefore, given the teachings of Mcfeely, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Mcfeely by employing the curved bottom surface for the third metal layer, as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
Allowable Subject Matter
Claims 8-9 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 8, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the silicide layer comprises a concave upper surface and a convex bottom surface.
With respect to claim 9, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the liner layer comprises a slanted side portion and a curved bottom portion.
With respect to claim 20, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein an interface between the silicide layer and the barrier layer is curved.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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September 19, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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