DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is not clear what the claimed limitation “a metal-free dielectric material” suggests, because Applicants did not specifically disclose the definition of “metal-free”, for example, 0% of metal impurities or 0.0001% of metal impurities, and Applicants did not originally disclose and do not claim what kind of metal elements should not be present in the claimed upper portion; in this case, if the claimed term “metal-free” suggests absolute 0% of metal impurities in a dielectric material and thus 100% pure dielectric material, such a dielectric material would not exist in reality, naturally or artificially, since there are always some degree of, albeit small, impurities including metal impurities in any component layer of a semiconductor device, especially in a silicon-containing layer since, during a manufacturing process of a silicon ingot, alkali metals such as Na and K would be introduced into the silicon to some degree; furthermore, the claimed “metal-free” dielectric material layer 140L is in contact with a metal oxide layer 740 shown in Fig. 8 of current application, and therefore, metal atoms contained in the metal oxide layer would diffuse into the dielectric material layer due to interdiffusion of metallic atoms in the final product of the claimed semiconductor device, which is well known in the art, therefore, the dielectric material layer would not be “metal-free” in the claimed semiconductor device; please also note that metal atoms such as Au are highly mobile in a semiconductor device structure, and therefore, the originally intended “metal-free” dielectric material would also be contaminated with metal impurities to some degree as the semiconductor device is being used. Claims 2-7 depend on claim 1, therefore, claims 2-7 are also indefinite.
Regarding claim 8, it is not clear what the claimed limitation “a metal-free first dielectric layer” suggests, as the same reason discussed in claim 1 above. Claims 9-14 depend on claim 8, therefore, claims 9-14 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-7 and 15-16 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Shu et al. (US 2021/0217887, hereinafter Shu).
Regarding claim 1, Shu discloses A semiconductor structure, comprising:
a substrate (substrate 102, Fig. 11);
first and second fin structures (fin 103A and 103B, Fig. 11) formed on the substrate (102, Fig. 11); and
an isolation structure (first insulating material layer 110/second insulating material layer 112/layer of insulating material 125, Fig. 11) between the first and second fin structures (between 103A and 103B, Fig. 11),
wherein the isolation structure (110/112/125, Fig. 11) comprises:
a lower portion (lower portion of 110, Fig. 11) comprising a metal-free dielectric material, because “the first insulating material layer 110 may be comprised of a variety of different insulating materials, e.g., silicon dioxide, an HDP oxide, a HARP oxide, etc” (emphasis added, [0022]), and the claimed limitation, “a metal-free”, is discussed in 35 U.S.C. 112(b) rejections above. Examiner notes that the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, therefore, within the first insulating material layer 110 by Shu, a lower portion of the first insulating material layer 110 may correspond to the claimed lower portion; and
an upper portion (upper portion of 110 and upper portion of 112, see attached and annotated Fig. 11 below) comprising a metallic element, because “the second insulating material layer 112 may be made of aluminum oxide (Al2O3)” (emphasis added, [0034]), therefore, the upper portion of 110 and 112 includes a metallic element – aluminum. Examiner notes that the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, therefore, within the first insulating material layer 110 by Shu, an upper portion of the first insulating material layer 110 may correspond to the claimed upper portion.
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Regarding claim 3, Shu further discloses for the semiconductor structure of claim 1 that the metal-free dielectric material (lower portion of 110, Fig. 11) comprises silicon with an atomic concentration less than 50%, because the first insulating material layer 110 by Shu includes silicon dioxide (SiO2, [0022]) and the stoichiometric silicon dioxide contains 33.3 atomic concentration, and wherein the upper portion of the isolation structure (upper portion of 110 and 112, Fig. 11) further comprises oxygen, because the upper portion of the first and second insulating material layers includes silicon dioxide ([0022]) and aluminum oxide ([0034]), respectively, therefore, it includes oxygen.
Regarding claim 4, Shu further discloses for the semiconductor structure of claim 1 that a height of the first fin structure (height of 103A, Fig. 11) is less than a separation between the substrate (102, Fig. 11) and a top of the isolation structure (top surface of 125, Fig. 11).
Regarding claim 5, Shu further discloses for the semiconductor structure of claim 1 that a height of the first fin structure (height of 103A, Fig. 11) is greater than a separation between a bottom of the upper portion of the isolation structure (bottom of the upper portion of 110/112, see attached Fig. 11 above) and the substrate (102, Fig. 11).
Regarding claim 6, Shu further discloses for the semiconductor structure of claim 1, further comprising that a layer of insulating material (conformal liner layer 108, Fig. 11) between the substrate (102, Fig. 11) and the isolation structure (110/112/125, Fig. 11).
Regarding claim 7, Shu further discloses for the semiconductor structure of claim 1, further comprising that another isolation structure (sidewall spacer 122, Fig. 11) disposed between the first fin structure (103A, Fig. 11) and the isolation structure (110/112/125, Fig. 11), because the sidewall spacer 122 by Shu is formed between the fin 103A and the layer of insulating material 125, therefore, the sidewall spacer 122 can correspond to the claimed another isolation structure, wherein a height of the isolation structure (height of 110/112/125, i.e., distance from the bottom surface of 112 to the top surface of 125, Fig. 11) is greater than a height of the other isolation structure (height of 122, i.e., distance from the bottom surface of 122 to the top surface of 122, Fig. 11).
Regarding claim 15, Shu further discloses A structure, comprising:
first and second fin structures (103A and 103B, Fig. 11) on a substrate (102, Fig. 11);
a gate structure (gate insulating layer 120A/gate electrode 120B, Fig. 11) comprising a first portion (left portion of 120A/120B, Fig. 11) surrounding the first fin structure (103A, Fig. 11) and a second portion (right portion og 120A/120B, Fig. 11) surrounding the second fin structure (103B, Fig. 11); and
an isolation structure (composite structure of 110/112/125, Fig. 11), between the first and second fin structures (between 103A and 103B, Fig. 11), comprising:
a first layer of dielectric material (first insulating material layer 110, Fig. 11) between the first and second fin structures (between 103A and 103B, Fig. 11); and
a second layer of dielectric material (layer of insulating material 125, Fig. 11) over the first layer of dielectric material (over 110, Fig. 11).
Regarding claim 16, Shu further discloses for the structure of claim 15, further comprising that an insulating material layer (conformal liner layer 108, Fig. 11) between the substrate (102, Fig. 11) and the isolation structure (110/112/125, Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 11-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over by Chung (US 2020/0052081) in view of Shu et al. (US 2021/0217887, hereinafter Shu).
Regarding claim 8, Chung discloses A structure, comprising:
a fin structure (fin 310, Fig. 6A) on a substrate (substrate 110, Fig. 6A);
a hard mask layer (second mask patterns 210, Fig. 6A) disposed on a top surface of the fin structure (top surface of 310, Fig. 6A);
a seed layer (first dielectric layer 412, Fig. 6A) disposed on sidewalls of the fin structure (sidewall of 310, Fig. 6A), because Applicants do not specifically claim what the seed layer is made of and/or what the claimed seed layer serves as a seed for, the first dielectric layer 412 by Chung is disposed directly on sidewalls of the fin 310 (Fig. 6A), therefore, the first dielectric layer 412 can correspond to the seed layer in the claimed invention;
a capping layer (second dielectric layer 414, Fig. 6A) disposed on sidewall surfaces of the seed layer (sidewall surface of 412, Fig. 6A); and an isolation structure (isolation material 500, Fig. 7) in contact with the capping layer (414, Fig. 7).
Chung does not explicitly disclose that the isolation structure comprising a metal-free first dielectric layer and a second dielectric layer comprising metal.
However, Shu discloses FinFET structures including a first and second insulating material layer 110 and 112, and a layer of insulating material 125 formed between the fins 103A and 103B (Fig. 11), and therefore, a composite structure of 110/112/125 corresponds to the claimed isolation structure. Accordingly, the first and second insulating material layer 110 and 112 correspond to the claimed metal-free first dielectric layer and the claimed second dielectric layer, respectively. Shu further teaches that the first insulating material layer 110 is made of silicon dioxide ([0022]) and the second insulating material layer 112 is made of aluminum oxide ([0034]), therefore, the second insulating material layer 122 by Shu comprises a metallic element aluminum. The claimed limitation, “a metal-free” is discussed in 35 U.S.C. 112(b) rejections above.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the isolation structure with multi-layers of insulating material of Shu into the FinFET structure taught by Chung, in order to improve electrical properties of FinFET device.
Regarding claim 11, Shu further discloses that a height of the fin structure (height of 103A, Fig. 11) is less than a separation between the substrate (102, Fig. 11) and a top of the isolation structure (top of 125, Fig. 11).
Regarding claim 12, Shu further discloses that a gate structure (gate insulation layer 120A/gate electrode 120B, Fig. 11), wherein the fin structure (103A, Fig. 11) extends along a first direction (vertical direction, Fig. 11), and wherein: the gate structure (120A/120B, Fig. 11) is disposed on the fin structure (103A, Fig. 11) and extends along a second direction (lateral direction, Fig. 11) perpendicular to the first direction (vertical direction, Fig. 11), and the isolation structure (composite structure of 110/112/125, Fig. 11) is disposed on the gate structure (120A/120B, Fig. 11) and extends along the first direction (vertical direction, Fig. 11), because, the composite structure of 110/112/125 is disposed on the side surfaces of the gate electrode 120B (Fig. 11).
Regarding claim 14, Shu further discloses that an insulating material layer (conformal liner layer 108, Fig. 11) between the substrate (102, Fig. 11) and the isolation structure (composite structure of 110/112/125, Fig. 11).
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over by Shu et al. (US 2021/0217887, hereinafter Shu) in view of Chung (US 2020/0052081).
Regarding claim 17, Shu does not explicitly disclose that a hard mask layer disposed on top of the first fin structure and the second fin structure; and a seed layer surrounding the first fin structure and the second fin structure.
However, Chung discloses FinFET structure including the second mask patterns 210 disclosed on top of the fins 310 (Fig. 6A), therefore, the second mask patterns 210 can correspond to the claimed hard mask layer, and because Applicants do not specifically claim what a seed layer is made of and/or what the claimed seed layer serves as a seed for, the first dielectric layer 412 by Chung surrounds the fins 310 (Fig. 6A), therefore, the first dielectric layer 412 can correspond to the seed layer in the claimed invention.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the hard mask layer and insulating seed layer disclosed by Chung into the FinFET structure taught by Shu, in order to improve electrical properties of FinFET device.
Regarding claim 19, Chung further discloses that a capping layer (second dielectric layer 414, Fig. 6A) disposed on sidewall surfaces of the seed layer (sidewall surface of first dielectric layer 412, Fig. 6A).
Regarding claim 20, Shu further discloses that a width of the isolation structure is less than a separation between the first and second fin structures (distance between 103A and 103B, Fig. 11), because Applicants do not specifically claim a width of an entirety of the isolation structure is less than the separation, the recited “a width” may correspond to the width of the first insulating material layer 110 and it is less than the distance between the fin 103A and 103B (Fig. 11).
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this office action do not teach the claimed limitation, “a top surface of second layer of dielectric material is substantially coplanar with a top surface of the hard mask layer”.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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