DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application discloses and claims only subject matter disclosed in prior Application No. 17/125,688 (‘688 application), filed 12/17/2020, now U.S. Patent No. 12,707,619 (‘619 patent), and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application constitutes a divisional.
This divisional does not automatically receive safe-harbor protection against claim 17 of the ‘619 patent because it is styled as a divisional. Original group III was non-elected in a restriction requirement of U.S. Patent Application No. 17/125,688 and it included the memory system/array + pre-charge circuit invention presented by independent claim 21. Allowing claim 36/issued claim 17 (introduced after Group I was elected), was labeled as a memory system in the elected ‘688 application, and appears potentially to have crossed the restriction boundary. The scope of issued claim 17 falls on the side of the original restriction. See MPEP 804.01 regarding consonance requiring maintaining the line of demarcation between the restricted invention. Accordingly, this divisional is not shielded from a double patenting rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-20 of U.S. Patent No. 12,707,619 in view of U.S. Patent No. U.S. Patent Application Publication No. 2007/0268738 (Heinrich-Barna).
Pending claim
‘619 patent
Heinrich-Barna
17. an array of memory cells comprising a first memory cell and a second memory cell
17. a memory array comprising a memory cell with a first bitline node and a second bitline node; and a pre-charge circuit coupled to the memory array and comprising: a first transistor device coupled to a power supply voltage and comprising a first gate terminal configured to receive a control signal that transitions from a first value to a second value at the first gate terminal; a second transistor device coupled to the power supply voltage and comprising a second gate terminal configured to receive the control signal that transitions from the first value to the second value at the second gate terminal;
a pre-charge circuit coupled to the array of memory cells and comprising a first pre-charge cell, a second pre-charge cell, and a first write assist circuit, and a second write assist circuit, the first pre-charge cell and the second pre-charge cell are configured to charge bitlines of the first memory cell and the second memory cell, respectively, to a first voltage;
a first pass device comprising a third gate terminal configured to cause the first pass device to pass the power supply voltage from the first transistor device to the first bitline node based on the control signal transitioning from the first value to the second value at the third gate terminal; and a second pass device comprising a fourth gate terminal configured to cause the second pass device to pass the power supply voltage from the second transistor device to the second bitline node based on the control signal transitioning from the first value to the second value at the fourth gate terminal,
maintaining bitline 22 at a precharged voltage near high-voltage rail 36 ([0016])
the first write assist circuit and the second write assist circuit are configured to set the bitlines of the first memory cell and the second memory cell, respectively, to a second voltage lower than the first voltage
write assist circuit 14 coupled to bitline 22, first discharging bitline 22 toward low-voltage rail 38 and then producing a voltage below that rail 38
([0014], [0018, [0019], [0023]-[0025])
Accordingly, pending claim 17 would have been an obvious variation of the ‘619 patent claim 17 in view of Heinrich-Barna.
Likewise, pending claim 9 limitations of an array of memory cells and the pre-charge circuit are also met by the memory array of the ‘619 patent claim 17. In Heinrich-Barna, the bitline 22 provides further support, and the write-assist circuit 14 discharges the precharged bitline 22 toward low-voltage rail 38 and may pull it below that rail 38. Accordingly, pending claim 9 would have been an obvious variation of the ‘619 patent claim 17 in view of Heinrich-Barna.
In addition, pending claim 1 limitations that are met by the ‘619 patent claim 17 include first and second bitline nodes, first and second transistor / pass device paths for supplying the pre-charge voltage. Heinrich-Barna teaches multiple SRAM bit cells and respective bitlines, each bitline being associated with write-driving circuitry, and teaches applying write-assist voltage reduction to the SRAM bitline during writing. The duplication of the known pre-charge / write-assist arrangement for respective bitlines / memory cells would have been an obvious implementation of the same known SRAM write-assist technique, providing the known write-assist function to each respective bitline. Accordingly, pending claim 1 would have been an obvious variation of the ‘619 patent claim 17 in view of Heinrich-Barna.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory system of claim 17 of the ‘619 patent to include write-assist circuitry. The motivation would be lowering the voltage of a precharged bitline during a write operation to improve the ability to write date to the SRAM memory cell as taught by Heinrich-Barna.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 4, 11, 12 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for a single stacked configuration (claim 3), does not reasonably provide enablement for a first and second stacked configuration. Also, there is no enablement for “the other pre-charge cell is between the pre-charge cell and the write assist circuit in a stacked configuration” (claim 11). The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims. In paragraph [0065] of the application as filed, “write assist cell 830 and pre-charge cells 4150 and 4151 can be arranged in a stacked configuration and coupled to a bitline pair BL/BLB of a memory cell (e.g., memory cell 190).” Accordingly, support can only be found for one stacked configuration and two stacked pre-charge cells below a write assist cell.
Claims 4 and 12 are rejected as being dependent on a non-enabling base claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 12 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "rows and columns" in lines 3-4 and “a first row…, a first column…, and a second column.” There is insufficient antecedent basis for the first row and the first and second columns limitation in the claim.
Claim 12 recites the limitation “coupled…to a plurality of rows.” The relationship between the write assist circuit and the plurality of rows is unclear.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 9, 10, 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2017/0200490 (Ngo) in view of U.S. Patent Application Publication No. 2014/0269105 (Dubey).
Ngo discloses (at least Figs. 4, 5)
1. A system, comprising:
an array of memory cells 400 comprising a first memory cell and a second memory cell 401a-401d; and
a pre-charge circuit 500 coupled to the array of memory cells 400 and comprising a first pre-charge cell, a second pre-charge cell, and a first write assist circuit, and a second write assist circuit 402a-402d, 403a-403d, wherein:
the first pre-charge cell and the second pre-charge cell 402a-402d, 403a-403d are configured to charge bitlines 501 (bl, bl_b) of the first memory cell and the second memory cell 401a-401d, respectively, to a first voltage VccSram (blpch_b).
Ngo fails to disclose
the first write assist circuit and the second write assist circuit are configured to set the bitlines of the first memory cell and the second memory cell, respectively, to a second voltage lower than the first voltage.
Dubey teaches
A system comprising:
a memory cell array 101-104;
the first write assist circuit and the second write assist circuit 120 (duplication of parts see MPEP 2144.04) are configured to set the bitlines BB0/BT0-BB3/BT3 of the first memory cell and the second memory cell 101-104, respectively, to a second voltage lower Vnbl than the first voltage VSS ([0030]-[0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the local write-assist logic units of Ngo to include negative-bitline write-assist circuitry. The motivation would be so that the bitlines are set to a voltage lower than the precharge voltage during a write operation to improve the ability to write data into a SRAM memory cell and improve write margin as taught by Dubey ([0046]). Further, improvements include the signal-to-noise margin of unselected cells, avoiding half selected cells that results in an unstable condition, and avoiding unnecessary parasitic capacitance on the bitlines during a read operation.
The combination of references teaches
2. The system of claim 1, wherein the array of memory cells 400 are arranged in rows of memory cells and columns of memory cells (Ngo, [0038]), and wherein: the first pre-charge cell and the first write assist circuit are coupled to bitlines 501 of memory cells in a first column of memory cells; and the second pre-charge cell and the second write assist circuit are coupled to bitlines of memory cells in a second column of memory cells (403a-403d coupled to 501).
Ngo discloses (at least Figs. 4, 5)
9. A system, comprising:
an array of memory cells 400; and
a pre-charge circuit 500 coupled to the array of memory cells 400 and comprising:
a pre-charge cell 500 configured to charge a bitline 501 (bl, bl_b) in the array of memory cells 400 to a first voltage VccSram (blpch_b).
Ngo fails to disclose
a write assist circuit configured to set the bitline in the array of memory cells to a second voltage lower than the first voltage.
Dubey teaches
A system comprising:
a memory cell array 101-104;
a write assist circuit 120 configured to set the bitline BB0/BT0-BB3/BT3 in the array of memory cells 101-104 to a second voltage lower Vnbl than the first voltage VSS ([0030]-[0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the local write-assist logic units of Ngo to include negative-bitline write-assist circuitry. The motivation would be so that the bitlines are set to a voltage lower than the precharge voltage during a write operation to improve the ability to write data into a SRAM memory cell and improve write margin as taught by Dubey ([0046]). Further, improvements include the signal-to-noise margin of unselected cells, avoiding half selected cells that results in an unstable condition, and avoiding unnecessary parasitic capacitance on the bitlines during a read operation.
The combination of references teaches
10. The system of claim 9, wherein the array of memory cells 400 are arranged in rows of memory cells and columns of memory cells (Ngo, [0038]), and wherein the pre-charge cell 500 and the write assist circuit 120 (Dubey) are coupled to the bitline 501 in a column of memory cells.
Ngo discloses (at least Figs. 4, 5)
17. A system, comprising:
a plurality of memory cells 400;
a pre-charge cell 500 configured to charge a bitline 501 (bl, bl_b) coupled to the plurality of memory cells 400 to a first voltage VccSram (blpch_b).
Ngo fails to disclose
a write assist circuit configured to set the bitline coupled to the plurality of memory cells to a second voltage lower than the first voltage.
Dubey teaches
A system comprising:
a memory cell array 101-104;
a write assist circuit 120 configured to set the bitline BB0/BT0-BB3/BT3 in the array of memory cells 101-104 to a second voltage lower Vnbl than the first voltage VSS ([0030]-[0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the local write-assist logic units of Ngo to include negative-bitline write-assist circuitry. The motivation would be so that the bitlines are set to a voltage lower than the precharge voltage during a write operation to improve the ability to write data into a SRAM memory cell and improve write margin as taught by Dubey ([0046]). Further, improvements include the signal-to-noise margin of unselected cells, avoiding half selected cells that results in an unstable condition, and avoiding unnecessary parasitic capacitance on the bitlines during a read operation.
The combination of references teaches
18. The system of claim 17, wherein the plurality of memory cells 400 are arranged in rows of memory cells and columns of memory cells (Ngo, [0038]), and wherein the pre-charge cell and the write assist circuit 120 (Dubey) are coupled to the bitline 501 in a column of memory cells.
Claim(s) 5, 6, 13, 14, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ngo in view of Dubey as applied to claims 1, 9, 17 above, and further in view of U.S. Patent Application Publication No. 2005/0073893 (Chen ‘893).
The combination of references fails to teach
5. The system of claim 1, wherein each of the first and second pre-charge cells comprises: a first transistor configured to pass the first voltage to a first circuit node electrically coupled to a first bitline of the first memory cell or a second bitline of the second memory cell; and a second transistor configured to pass the first voltage to a second circuit node electrically coupled to a complement of the first bitline of the first memory cell or a complement of the second bitline of the second memory cell.
The combination of references fails to teach
6. The system of claim 5, wherein each of the first and second pre-charge cells further comprises: a first pass transistor configured to pass the first voltage from the first circuit node to the first bitline of the first memory cell or the second bitline of the second memory cell; and a second pass transistor configured to pass the first voltage from the second circuit node to the complement of the first bitline of the first memory cell or the complement of the second bitline of the second memory cell.
The combination of references fails to teach
13. The system of claim 9, wherein the pre-charge cell comprises: a first transistor configured to pass the first voltage to a first circuit node electrically coupled to the bitline; and a second transistor configured to pass the first voltage to a second circuit node electrically coupled to a complement of the bitline.
The combination of references fails to teach
14. The system of claim 13, wherein the pre-charge cell further comprises: a first pass transistor configured to pass the first voltage from the first circuit node to the bitline; and a second pass transistor configured to pass the first voltage from the second circuit node to the complement of the bitline.
The combination of references fails to teach
19. The system of claim 17, wherein the pre-charge cell comprises: a first transistor configured to pass the first voltage to a first circuit node electrically coupled to the bitline; and a second transistor configured to pass the first voltage to a second circuit node electrically coupled to a complement of the bitline.
Chen ‘893 teaches (at least Fig. 2)
A system comprising:
a pre-charge circuit 200 including:
a first transistor M5 configured to pass the first voltage Vcc to a first circuit node (the junction of M5 and M3) electrically coupled to a first bitline 115 of the first memory cell or a second bitline 120 of the second memory cell; and
a second transistor M6 configured to pass the first voltage Vcc to a second circuit node (the junction of M6 and M4) electrically coupled to a complement of the first bitline 115 of the first memory cell or a complement of the second bitline 120 of the second memory cell.
For claim 6, M3 is the first pass transistor and the circuit node is the junction of M5 and M3; M4 is the second pass transistor and the circuit node is the junction of M6 and M4.
For claim 13, M5 passes to M5/M3 junction; M6 passes to the M6/M4 junction.
For claim 14, M3 passes to M5/M3 junction; M4 passes to M6/M4 junction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a series precharge-enable and precharge transistor arrangement in the modified system of Ngo. The motivation would be additional precharge-enable transistors permit selective isolation of a defective precharge path while allowing normal precharge operation when enable, thereby reducing leakage associate with a defective memory column as taught by Chen ‘893 ([0007], [0008]).
Claim(s) 7, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over 5Ngo in view of Dubey as applied to claims 1, 9 above, and further in view of U.S. Patent Application Publication No. 2016/0196868 (Huang).
The combination of references fails to teach
7. The system of claim 6, wherein each of the first and second pre-charge cells further comprises: a third transistor configured to pull the first circuit node to the second voltage in response to being activated; and a fourth transistor configured to pull the second circuit node to the second voltage in response to being activated.
The combination of references fails to teach
15. The system of claim 14, wherein the pre-charge cell further comprises: a third transistor configured to pull the first circuit node to the second voltage in response to being activated; and a fourth transistor configured to pull the second circuit node to the second voltage in response to being activated.
Huang teaches (at least Figs. 3A, 3B)
A system comprising:
a third transistor 282 configured to pull the first circuit node N1 to the second voltage in response to being activated (source coupled to N3, gate controlled by bitline BLB); and a fourth transistor 284 configured to pull the second circuit node N2 to the second voltage in response to being activated (drain coupled to N3, gate controlled by bitline BL).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use pull-down transistors for the first and second nodes in the modified system of Ngo. The motivation would lower the voltage of a corresponding precharged node during a write operation, which improves SRAM write operation and helps overcome write failure while maintaining the other node at the supply voltages as taught by Huang ([0006], [0022]-[0024]).
Claim(s) 8, 16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ngo in view of Dubey as applied to claims 1, 14, 17 above, and further in view of U.S. Patent No. 9,741,429 (Chen ‘429).
The combination of references fails to teach
8. The system of claim 1, wherein each of the first and second write assist circuits comprises: a first transistor configured to pass the second voltage to a first circuit node in response to being activated; a second transistor configured to pass the second voltage to a second circuit node in response to being activated; a third transistor configured to pass the second voltage from the first circuit node to a first bitline of the first memory cell or a second bitline of the second memory cell; and a third transistor configured to pass the second voltage from the second circuit node to a complement of the first bitline of the first memory cell or a complement of the second bitline of the second memory cell.
The combination of references fails to teach
16. The system of claim 9, wherein the write assist circuit comprises: a first transistor configured to pass the second voltage to a first circuit node in response to being activated; a second transistor configured to pass the second voltage to a second circuit node in response to being activated; a third transistor configured to pass the second voltage from the first circuit node to the bitline; and a third transistor configured to pass the second voltage from the second circuit node to a complement of the bitline.
The combination of references fails to teach
20. The system of claim 17, wherein the write assist circuit comprises: a first transistor configured to pass the second voltage to a first circuit node in response to being activated; a second transistor configured to pass the second voltage to a second circuit node in response to being activated; a third transistor configured to pass the second voltage from the first circuit node to the bitline; and a third transistor configured to pass the second voltage from the second circuit node to a complement of the bitline.
Chen ‘429 teaches (at least Fig. 4)
A system comprising:
wherein each of the first and second write assist circuits 410 (including pull-down circuits 4120 - 412N and columns 1700 - 170N) comprises: a first transistor (pull-down transistor within inverter 424) configured to pass the second voltage NVSS to a first circuit node BL’ 430 in response to being activated; a second transistor (pull-down transistor within inverter 426) configured to pass the second voltage NVSS to a second circuit node BLB’ 440 in response to being activated; a third transistor 413 configured to pass the second voltage NVSS from the first circuit node BL’ 430 to a first bitline BL of the first memory cell or a second bitline of the second memory cell; and a fourth transistor 414 configured to pass the second voltage NVSS from the second circuit node BLB’ 440 to a complement of the first bitline BL of the first memory cell or a complement of the second bitline BLB of the second memory cell.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use two-stage write-assist paths in the modified system of Ngo. The motivation would be applying a negative write-assist voltage to a selected bitline improves SRAM writability as taught by Chen ‘429. Further, repeating write-assist pull-down circuitry for respective memory columns would provide the same write-assist function to each selected column.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2017/0243635 (Sonkar), 2018/0301185 (Lin), 2015/0255148 (Roy) teach using a pre-charge circuit to set bitlines to a known voltage before reading or writing memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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