CTNF 18/789,569 CTNF 98637 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 15, lines 1 and 2, recites “wherein forming etching the top surface of the substrate comprises,” which is indefinite due to improper composition and a lack of clarity as to whether the top surface of the substrate is being formed or etched. For the purpose of compact prosecution, the claim will be interpreted as “wherein etching the top surface of the substrate comprises.” Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-4 and 6-10 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Cheng et al. (US20190067452A1) . Regarding claim 1, Cheng teaches a method, comprising: depositing a plurality of alternating layers of first and second semiconductor layers (110, 112) on a substrate (102), wherein the substrate (102) comprises germanium {Figs. 1A-1, 1A-2, 4; [0019, 0023]}; forming a source/drain region (132B) in contact with the plurality of first and second semiconductor layers (110, 112) {Figs. 1B-1, 1B-2, 4B; [0049]}; removing first semiconductor layers (112) to form a plurality of first openings between the plurality of second semiconductor layers (110) and a second opening between a bottom-most second semiconductor layer (110) and the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copies of Cheng’s Figs. 3E-1, 3E-2 below; second opening is between lowermost 110 and 102 along a diagonal line}; removing an upper portion of the substrate (102) through the second opening to form a third opening that extends below a top surface of the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copies of Cheng’s Figs. 3E-1, 3E-2 below}; forming a gate structure (162, 164) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}, comprising: forming a first portion (portion of 162, 164 within first openings) of the gate structure (162, 164) within each of the first openings of the plurality of openings {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}; and forming a second portion (portion of 162, 164 within third opening) of the gate structure (162, 164) within the third opening {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}. PNG media_image1.png 314 447 media_image1.png Greyscale PNG media_image2.png 315 417 media_image2.png Greyscale Regarding claim 2, Cheng teaches the method of claim 1, and Cheng further teaches further comprising removing side portions of the first semiconductor layers (112) to form recesses on either side of the first semiconductor layers (112) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}. PNG media_image3.png 314 517 media_image3.png Greyscale Regarding claim 3, Cheng teaches the method of claim 2, and Cheng further teaches further comprising forming a plurality of inner spacers in the recesses on either side of the first semiconductor layers (112) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below; inner spacers formed by residual material of 112 within 132A after the removal of other material of 112 to create recesses}. PNG media_image4.png 314 565 media_image4.png Greyscale Regarding claim 4, Cheng teaches the method of claim 3, and Cheng further teaches wherein removing the upper portion of the substrate (102) through the second opening comprises removing a portion of the substrate (102) under (e.g., lower position) a bottom-most inner spacer of the plurality of inner spacers {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}. PNG media_image5.png 314 553 media_image5.png Greyscale Regarding claim 6, Cheng teaches the method of claim 1, and Cheng further teaches wherein forming the first and second portions of the gate structure (162, 164) comprises depositing, within the first and third openings, gate layers (164) comprising a gate dielectric layer (162), a work function layer (work function layer), and a gate electrode layer (gate electrode layer) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0148, 0165]}. Regarding claim 7, Cheng teaches the method of claim 1, and Cheng further teaches further comprising forming the plurality of first semiconductor layers (112) of a material same as a material of the upper portion of the substrate (102) {[0019, 0024]}. Regarding claim 8, Cheng teaches the method of claim 1, and Cheng further teaches further comprising: depositing the plurality of first semiconductor layers (112) comprising silicon germanium {[0024]}; and depositing the plurality of second semiconductor layers (110) comprising silicon {[0024]}. Regarding claim 9, Cheng teaches the method of claim 1, and Cheng further teaches further comprising: depositing the plurality of first semiconductor layers (112) comprising silicon {[0024]}; and depositing the plurality of second semiconductor layers (110) comprising silicon germanium {[0024]}. Regarding claim 10, Cheng teaches the method of claim 1, and Cheng further teaches wherein removing the upper portion of the substrate (102) through the second opening comprises etching the substrate (102) to form the third opening with an oval-shaped cross-sectional area {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below} . PNG media_image6.png 405 610 media_image6.png Greyscale Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 11-17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Balakrishnan et al. (US20180083113A1) . Regarding claim 11, Cheng teaches a method, comprising: depositing a plurality of alternating layers of first and second semiconductor layers (110, 112) on a substrate (102) {Figs. 1A-1, 1A-2, 4; [0019, 0023]}; etching the first semiconductor layers (112) to expose the second semiconductor layers (110), and a top surface of the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]}; etching the top surface of the substrate (102) to form an opening {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]}; and forming a gate structure (162, 164) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}, comprising: forming a first portion (portion of 162, 164 within first openings) of the gate structure (162, 164) wrapped around each of the second semiconductor layers (110) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}; and forming a second portion (portion of 162, 164 within third opening) of the gate structure (162, 164) within the opening {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}. Cheng does not teach: forming a plurality of inner spacers on sidewalls of the first semiconductor layers; etching the first semiconductor layers to expose the plurality of inner spacers; the opening extends under a bottom-most inner spacer of the plurality of inner spacers. In an analogous art, Balakrishnan teaches forming a plurality of inner spacers (180) on sidewalls of first semiconductor layers (130) {Fig. 8; [0069]}; and etching the first semiconductor layers (130) to expose the plurality of inner spacers (180) {Fig. 17; [0100, 0101]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s method based on the teachings of Balakrishnan, as identified above, to protect the ends of the sacrificial release layers … during subsequent etching . Balakrishnan [0079]. Moreover, all the claimed elements (e.g., inner spacers, sidewalls of semiconductor layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Balakrishnan) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. A consequence of this modification is that Cheng’s opening would extend under a bottom-most inner spacer of Balakrishnan’s plurality of inner spacers as they are integrated within Cheng’s structure. Regarding claim 12, Cheng as modified by Balakrishnan teaches the method of claim 11, and Cheng further teaches further comprising forming the first semiconductor layers (112) of a material same as a material of the top surface of the substrate (102) {[0019, 0024]}. Regarding claim 13, Cheng as modified by Balakrishnan teaches the method of claim 11, and Cheng further teaches wherein forming the first and second portions of the gate structure (162, 164) comprises depositing, within the opening, gate layers (164) comprising a gate dielectric layer (162), a work function layer (work function layer), and a gate electrode layer (gate electrode layer) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0148, 0165]}. Regarding claim 14, Cheng as modified by Balakrishnan teaches the method of claim 11, and Cheng further teaches wherein depositing the first and second semiconductor layers (110, 112) comprises depositing germanium layers and germanium tin alloy layers, respectively {[0024]}. Regarding claim 15, as interpreted in view of the indefiniteness rejection, Cheng as modified by Balakrishnan teaches the method of claim 11, and Cheng further teaches wherein etching the top surface of the substrate (102) comprises etching the substrate (102) to form the opening with an oval- shaped cross-sectional area {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below}. PNG media_image6.png 405 610 media_image6.png Greyscale Regarding claim 16, Cheng teaches a method, comprising: depositing first and second groups of semiconductor layers (portions of 110, 112 within 132A) to form a stack of alternating semiconductor layers (110, 112) on a substrate (102) {Figs. 1A-1, 1A-2, 4; [0019, 0023]}; removing the first group of semiconductor layers (portions of 112 within 132A), wherein a portion of a top surface of the substrate (102) and portions of the second group of semiconductor layers (portions of 110 within 132A) are exposed {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]}; forming an opening by etching the portion of the top surface of the substrate (102) that is exposed, wherein the opening extends below the top surface of the substrate (102) {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]}; and forming a gate structure (162, 164) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}, comprising: forming a first portion (portion of 162, 164 within first openings) of the gate structure (162, 164) wrapped around each semiconductor layer of the second group of semiconductor layers (portions of 110 within 132A) {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}; and forming a second portion (portion of 162, 164 within third opening) of the gate structure (162, 164) in the opening {Figs. 2J-1, 2J-2, 2K-1, 2K-2, 3J-1, 3J-2, 3K-1, 3K-2; [0150]}. Cheng does not teach: forming a plurality of spacers on sidewalls of the first group of semiconductor layers; removing the first group of semiconductor layers, wherein a portion of a top surface of the substrate and portions of the second group of semiconductor layers between the plurality of spacers are exposed; forming an opening by etching the portion of the top surface of the substrate that is exposed between the plurality of spacers. Balakrishnan teaches forming a plurality of spacers (180) on sidewalls of a first group of semiconductor layers (130) {Fig. 8; [0069]}; and removing the first group of semiconductor layers (130), such that portions of a second group of semiconductor layers (140) between the plurality of spacers (180) are exposed {Fig. 17; [0100, 0101]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s method based on the teachings of Balakrishnan, as identified above, to protect the ends of the sacrificial release layers … during subsequent etching . Balakrishnan [0079]. Moreover, all the claimed elements (e.g., inner spacers, sidewalls of semiconductor layers) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Balakrishnan) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Consequences of this modification are that: (1) Cheng’s portion of a top surface of the substrate and Cheng’s portions of the second group of semiconductor layers between Balakrishnan’s plurality of spacers would be exposed by Cheng’s removal of the first group of semiconductor layers and (2) Cheng’s opening formed by etching the portion of the top surface of the substrate that is exposed would be between Balakrishnan’s plurality of spacers. Regarding claim 17, Cheng as modified by Balakrishnan teaches the method of claim 16, and Cheng further teaches wherein depositing the first and second groups of semiconductor layers (portions of 110, 112 within 132A) comprises depositing silicon germanium layers and silicon layers, respectively {[0024]}. Regarding claim 19, Cheng as modified by Balakrishnan teaches the method of claim 16, and Cheng further teaches wherein depositing the first and second groups of semiconductor layers (portions of 110, 112 within 132A) comprises depositing germanium layers and germanium tin alloy layers, respectively {[0024]}. Regarding claim 20, Cheng as modified by Balakrishnan teaches the method of claim 16, and Cheng further teaches wherein forming the opening comprises forming the opening with a cross-sectional area having an oval shape {Figs. 2E-1, 2E-2, 3E-1, 3E-2; [0103, 0104]; see annotated copy of Cheng’s Fig. 3E-1 below} . PNG media_image6.png 405 610 media_image6.png Greyscale Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 5, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have the recited subject matter whereby “removing the upper portion of the substrate through the second opening comprises exposing a bottom surface of a bottom-most spacer of the plurality of inner spacers.” Regarding claim 18, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have the recited subject matter whereby “forming the opening comprises exposing a bottom surface of a bottom-most spacer of the plurality of spacers.” Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Naskar et al. (US20210202479A1) teaches an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack. But Naskar does not teach the above-identified features of claims 5 and 18 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.W.W./Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891 Application/Control Number: 18/789,569 Page 2 Art Unit: 2891 Application/Control Number: 18/789,569 Page 3 Art Unit: 2891 Application/Control Number: 18/789,569 Page 4 Art Unit: 2891 Application/Control Number: 18/789,569 Page 5 Art Unit: 2891 Application/Control Number: 18/789,569 Page 6 Art Unit: 2891 Application/Control Number: 18/789,569 Page 7 Art Unit: 2891 Application/Control Number: 18/789,569 Page 8 Art Unit: 2891 Application/Control Number: 18/789,569 Page 9 Art Unit: 2891 Application/Control Number: 18/789,569 Page 10 Art Unit: 2891 Application/Control Number: 18/789,569 Page 11 Art Unit: 2891 Application/Control Number: 18/789,569 Page 12 Art Unit: 2891 Application/Control Number: 18/789,569 Page 13 Art Unit: 2891 Application/Control Number: 18/789,569 Page 14 Art Unit: 2891
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