DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 3, 7, 12-13, 15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al. (US 20160380066 A1, hereinafter Lin).
Re: Independent Claim 1, Lin teaches a semiconductor device (Fig. 1G), comprising:
a channel layer (110 including a fin structure in [0007], Fig. 1G);
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Lin’s Figure 1G-Annotated.
an interfacial layer (120 dielectric material in [0010], Fig. 1G) disposed over the channel layer (110);
a gate dielectric layer (150 dielectric layer in [0016], Fig. 1G) disposed over the interfacial layer (120);
a bilayer cap structure (155-160 in [0017-0018], Fig. 1G) comprising:
a metal nitride layer (155 cap layer made of TiN in [0017], Fig. 1G) disposed over the gate dielectric layer (150); and
a shield layer (160 blocking layer made of TiN in [0018], Fig. 1G) disposed over the metal nitride layer (155);
a barrier layer (165 work function metal layer in [0019], Fig. 1G) disposed over the shield layer (160); and
a gate electrode layer (190 metal layer in [0023], Fig. 1G) disposed over the barrier layer (165),
wherein: the metal nitride layer (155) comprises TiN ([0017]), and the shield layer (160) comprises one selected from the group consisting of SiN, Ti, titanium silicide, and SixTiyNz, where 0 ≤ x < 0.75, 0 ≤ y ≤ 1, 0 ≤ z ≤ 0.7, and x+y+z=1 (made of TiN [0018]).
Re: Claim 3, Lin discloses the semiconductor device of claim 1, wherein: the shield layer (155) is partially crystalline or completely amorphous (after layer 155 is deposited by CVD process as a crystalline layer or amorphous, as known in the art, then forming the single layer 160 as partially crystalline or amorphous conformally to layer 155 in [0017,0018]); and a percentage of crystallinity of the shield layer is in a range from 0 % to 90 % (160 is partially crystalline or amorphous in [0018]).
Re: Claim 7, Lin discloses the semiconductor device of claim 1, wherein the shield layer (160), metal nitride layer (155), and gate dielectric layer (150) do not comprise fluorine (these layers do not include fluorine in [0016-18]) or comprise fluorine in an amount of less than 0.6 atomic %.
Re: Independent Claim 12, Lin teaches a semiconductor device (Fig. 1G), comprising:
a channel layer (110 including a fin structure in [0007], Fig. 1G);
an interfacial layer (120 dielectric material in [0010], Fig. 1G) disposed over the channel layer (110);
a gate dielectric layer (150 dielectric layer in [0016], Fig. 1G) disposed over the interfacial layer (120);
a metal nitride layer (155 cap layer made of TiN in [0017], Fig. 1G) disposed over the gate dielectric layer (150);
a shield layer (160 blocking layer made of TiN in [0018], Fig. 1G) disposed over the metal nitride layer (155);
a work function adjustment layer (165 work function metal layer in [0019], Fig. 1G) formed over the shield layer (160); and
a gate electrode layer (190 metal layer in [0023], Fig. 1G) disposed over the work function adjustment layer (165),
wherein the shield layer (160) is partially crystalline or completely amorphous (after layer 155 is deposited by CVD process as a crystalline layer or amorphous, as known in the art, then forming the single layer 160 as partially crystalline or amorphous conformally to layer 155 in [0017,0018]).
Re: Claim 13, Lin discloses the semiconductor device of claim 12, wherein the shield layer (160) comprises one selected from the group consisting of Si, SiC, SiCl, SiN, Ti, TiC, TiCl, TiSi, TiN, or SiTiN (made of TiN [0018]).
Re: Independent Claim 15, Lin teaches a semiconductor device (Fig. 1G), comprising:
a fin structure (110 including a fin structure in [0007], Fig. 1G) comprising a channel layer (110-channel);
an isolation insulating layer (120 dielectric material in [0010], Fig. 1G);
a gate dielectric layer (150 dielectric layer in [0016], Fig. 1G) disposed over the channel layer (110-channel);
a bilayer cap structure (155-160 in [0017-0018], Fig. 1G) comprising:
a metal nitride layer (155 cap layer made of TiN in [0017], Fig. 1G) disposed over the gate dielectric layer (150); and
a shield layer (160 blocking layer made of TiN in [0018], Fig. 1G) disposed over the metal nitride layer (155); and
a gate electrode layer (190 metal layer in [0023], Fig. 1G) disposed over the shield layer (160),
wherein:
the metal nitride layer (155) comprises TiN; and the shield layer (160) comprises SixTiyNz, where 0 ≤ x < 1, 0 ≤ y ≤ 1, 0 ≤ z < 1, and x+y+z=1 (made of TiN [0018]).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2,16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of
Kuo (US 20140167187 A1, hereinafter Kuo).
Re: Claim 2, Lin discloses the semiconductor device of claim 1,
Lin does not expressly disclose wherein: a thickness of the metal nitride layer is in a range from 0.3 nm to 30 nm; a thickness of the shield layer is in a range from 0.5 nm to 30 nm; and a thickness T1 of the metal nitride layer and a thickness T2 of the shield layer satisfy 0.05 ≤ T2/(T1+T2) < 0.85.
However, in the same semiconductor device field of endeavor, Kuo discloses a thickness of the metal nitride layer (28 made of TiN in [0022], Fig. 1) is in a range from 0.3 nm to 30 nm (thickness of 2nm (20A) in [0022]); a thickness of the shield layer (30 barrier/etch stop made of TaN in [0023], Fig. 1) is in a range from 0.5 nm to 30 nm (thickness of 2nm (20A) in [0022]); and a thickness T1 of the metal nitride layer and a thickness T2 of the shield layer satisfy 0.05 ≤ T2/(T1+T2) < 0.85 (the value is 0.5).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the thickness of the Lin’s metal nitride layer in a range from 0.3 nm to 30 nm; a thickness of the shield layer is in a range from 0.5 nm to 30 nm; and a thickness T1 of the metal nitride layer and a thickness T2 of the shield layer satisfy 0.05 ≤ T2/(T1+T2) < 0.85 according to the thickness of the Kuo’s metal nitride layer in order to have the predictable result of improving gate control of the channel ([0002], Kuo).
Re: Claim 16, Lin discloses the semiconductor device of claim 15,
Lin does not expressly disclose wherein a thickness T1 of the metal nitride layer and a thickness T2 of the shield layer satisfy 0.05 ≤ T2/(T1+T2) < 1.0.
However, in the same semiconductor device field of endeavor, Kuo discloses a thickness T1 (thickness of 2nm (20A) in [0022]) of the metal nitride layer (28 made of TiN in [0022], Fig. 1) and a thickness T2 (thickness of 2nm (20A) in [0022]) of the shield layer (30 barrier/etch stop made of TaN in [0023], Fig. 1) satisfy 0.05 ≤ T2/(T1+T2) < 1.0 (the value is 0.5).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Kuo’s feature of a thickness T1 of the metal nitride layer and a thickness T2 of the shield layer satisfy 0.05 ≤ T2/(T1+T2) < 1.0 to the Lin’s metal nitride layer in order to have the predictable result of improving the gate control of the channel ([0002], Kuo).
Claim(s) 4-6, 14 and 17-20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Huo et al. (US 20170170027 A1, hereinafter Huo).
Re: Claim 4, Lin discloses the semiconductor device of claim 1,
Lin does not expressly disclose wherein: the metal nitride layer, the shield layer and the gate dielectric layer each comprise fluorine; and an amount of fluorine in the gate dielectric layer is smaller than an amount of fluorine in the metal nitride layer and an amount of fluorine in the shield layer.
However, in the same semiconductor device field of endeavor, Hou discloses the metal nitride layer (508A a fluorinated barrier metal layer in [0037], Fig. 5D), the shield layer (508B a fluorinated barrier metal layer in [0037], Fig. 5D) and the gate dielectric layer (506A a fluorinated gate dielectric layer in [0037], Fig. 5D) each comprise fluorine ([0037]); and an amount of fluorine in the gate dielectric layer (506A) is smaller (as a diffusion process, after the fluorine and annealing process, layer 506A would have the smaller amount of fluorine than layers 508A and 508B, Fig. 5D) than an amount of fluorine in the metal nitride layer (508A) and an amount of fluorine in the shield layer (508B).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Huo’s feature of the metal nitride layer, the shield layer and the gate dielectric layer each comprise fluorine; and an amount of fluorine in the gate dielectric layer is smaller than an amount of fluorine in the metal nitride layer and an amount of fluorine in the shield layer to Lin’s device in order to have the predictable result of effectively passivating interfacial and/or bulk defects of the high-K gate stack by way of the diffused fluorine atoms ([0036], Huo).
Re: Claim 5, Lin modified by Huo discloses the semiconductor device of claim 4, wherein: the shield layer (160, Lin) comprises fluorine in an amount of 0.02 atomic% to 75 atomic%; the metal nitride layer (155, Lin) comprises fluorine in an amount of 0.02 atomic% to 55 atomic%; and the gate dielectric layer (150, Lin) comprises fluorine in an amount of 0.01 atomic% to 40 atomic%.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the shield layer comprises fluorine in an amount of 0.02 atomic% to 75 atomic%; the metal nitride layer comprises fluorine in an amount of 0.02 atomic% to 55 atomic%; and the gate dielectric layer comprises fluorine in an amount of 0.01 atomic% to 40 atomic% because the concentration of fluorine can be controlled by the flow rate of the fluorine gas, the duration of the treatment and the temperature, in addition, post process such annealing treatment can be also adjusted. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. (MPEP 2144.05 (II)).
Re: Claim 6, Lin modified by Huo discloses the semiconductor device of claim 4, further comprising gate sidewall spacers (130 sidewall spacers in [0013], Fig. 1G, Lin) comprising a silicon-based insulating material (a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof in [0013]) and including fluorine.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have gate sidewall spacers including fluorine because the concentration of fluorine can be controlled by the flow rate of the fluorine gas, the duration of the treatment and the temperature, in addition, post process such annealing treatment can be also adjusted, then the diffusion to fluorine to the sidewall spacers is a results of the tune of the fluorine treatment. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. (MPEP 2144.05 (II)).
Re: Claim 14, Lin discloses the semiconductor device of claim 13,
Lin does not expressly disclose wherein: the metal nitride layer, the shield layer and the gate dielectric layer each comprise fluorine; and an atomic percentage of fluorine in the gate dielectric layer is less than an atomic percentage of fluorine in the metal nitride layer.
However, in the same semiconductor device field of endeavor, Hou discloses the metal nitride layer (508A a fluorinated barrier metal layer in [0037], Fig. 5D), the shield layer (508B a fluorinated barrier metal layer in [0037], Fig. 5D) and the gate dielectric layer (506A a fluorinated gate dielectric layer in [0037], Fig. 5D) each comprise fluorine ([0037]); and an amount percentage of fluorine in the gate dielectric layer (506A) is less (as a diffusion process, after the fluorine and annealing process, layer 506A would have the smaller amount of fluorine than layers 508A and 508B, Fig. 5D) than an atomic percentage of fluorine in the metal nitride layer (508A).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Huo’s feature of the metal nitride layer, the shield layer and the gate dielectric layer each comprise fluorine; and an atomic percentage of fluorine in the gate dielectric layer is less than an atomic percentage of fluorine in the metal nitride layer to Lin’s device in order to have the predictable result of effectively passivating interfacial and/or bulk defects of the high-K gate stack by way of the diffused fluorine atoms ([0036], Huo).
Re: Claim 17, Lin discloses the semiconductor device of claim 15,
Lin does not expressly disclose wherein: the metal nitride layer, the shield layer and the gate dielectric layer each comprise fluorine; and an amount of fluorine in the gate dielectric layer is smaller than an amount of fluorine in the metal nitride layer and an amount of fluorine in the shield layer.
However, in the same semiconductor device field of endeavor, Hou discloses the metal nitride layer (508A a fluorinated barrier metal layer in [0037], Fig. 5D), the shield layer (508B a fluorinated barrier metal layer in [0037], Fig. 5D) and the gate dielectric layer (506A a fluorinated gate dielectric layer in [0037], Fig. 5D) each comprise fluorine ([0037]); and an amount of fluorine in the gate dielectric layer (506A) is smaller (as a diffusion process, after the fluorine and annealing process, layer 506A would have the smaller amount of fluorine than layers 508A and 508B, Fig. 5D) than an amount of fluorine in the metal nitride layer (508A) and an amount of fluorine in the shield layer (508B).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Huo’s feature of the metal nitride layer, the shield layer and the gate dielectric layer each comprise fluorine; and an amount of fluorine in the gate dielectric layer is smaller than an amount of fluorine in the metal nitride layer and an amount of fluorine in the shield layer to Lin’s device in order to have the predictable result of effectively passivating interfacial and/or bulk defects of the high-K gate stack by way of the diffused fluorine atoms ([0036], Huo).
Re: Claim 18, Lin modified by Huo discloses the semiconductor device of claim 17, wherein the shield layer (160, Lin) comprises fluorine in an amount of 0.02 atomic % to 75 atomic %.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the shield layer comprises fluorine in an amount of 0.02 atomic % to 75 atomic % because the concentration of fluorine can be controlled by the flow rate of the fluorine gas, the duration of the treatment and the temperature, in addition, post process such annealing treatment can be also adjusted. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. (MPEP 2144.05 (II)).
Re: Claim 19, Lin modified by Huo discloses the semiconductor device of claim 17, wherein the metal nitride layer (155, Lin) comprises fluorine in an amount of 0.02 atomic % to 75 atomic %.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the metal nitride layer comprises fluorine in an amount of 0.02 atomic % to 75 atomic % because the concentration of fluorine can be controlled by the flow rate of the fluorine gas, the duration of the treatment and the temperature, in addition, post process such annealing treatment can be also adjusted. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. (MPEP 2144.05 (II)).
Re: Claim 20, Lin modified by Huo discloses the semiconductor device of claim 17, wherein the gate dielectric layer (150, Lin) comprises fluorine in an amount of 0.01 atomic % to 40 atomic %.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the gate dielectric layer comprises fluorine in an amount of 0.01 atomic % to 40 atomic % because the concentration of fluorine can be controlled by the flow rate of the fluorine gas, the duration of the treatment and the temperature, in addition, post process such annealing treatment can be also adjusted. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. (MPEP 2144.05 (II)).
Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Kim (US 20170053996 A1, hereinafter Kim).
Re: Claim 8, Lin discloses the semiconductor device of claim 1,
Lin does not expressly disclose wherein the shield layer comprises SiN.
However, in the same semiconductor device field of endeavor, Kim discloses wherein the shield layer (138 shield film in [0048], Fig. 4) comprises SiN (made of SiN in [0048]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Kim’s feature of wherein the shield layer comprises SiN to the Lin’s shield layer in order to have the predictable result of effectively protecting underlying layers of contaminants and the further etching process ([0048], Kim).
Claim(s) 9-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Wang et al. (US 9418853 B1, hereinafter Wang).
Re: Claim 9, Lin discloses the semiconductor device of claim 1,
Lin does not expressly disclose wherein the metal nitride layer comprises oxygen in an amount of 1.5 atomic% to 65 atomic%.
However, in the same semiconductor device field of endeavor, Wang discloses wherein the metal nitride layer (166 made of TiON in Col. 4 lines 2-6) comprises oxygen (having oxygen atoms absorbed from the air but it could be reduced by layer 174 in Col. 4 lines 2-6 and 8-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the metal nitride layer comprising oxygen in an amount of 1.5 atomic% to 65 atomic% because the concentration of oxygen can be controlled by the deposition of upper layer as showed in Wang’s device that reduce the amount of oxygen (in Col. 4 lines 8-10, Wang) in the metal nitride layer, then this can be adjusted according to the desired electrical properties of the device. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art (MPEP 2144.05 (II)).
Re: Claim 10, Lin discloses the semiconductor device of claim 1,
Lin does not expressly disclose wherein in the metal nitride layer, a ratio of a number of titanium atoms bonding to oxygen (Ti-O) to a number of titanium bonding to nitrogen (Ti-N) is in a range from 0.03 to 0.48.
However, in the same semiconductor device field of endeavor, Wang discloses wherein the metal nitride layer (166 made of TiON in Col. 4 lines 2-6) comprises oxygen (having oxygen atoms absorbed from the air but it could be reduced by layer 174 in Col. 4 lines 2-6 and 8-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have in the metal nitride layer, a ratio of a number of titanium atoms bonding to oxygen (Ti-O) to a number of titanium bonding to nitrogen (Ti-N) is in a range from 0.03 to 0.48 because the concentration of oxygen can be controlled by the deposition of upper layer as showed in Wang’s device that reduce the amount of oxygen (in Col. 4 lines 8-10, Wang) in the metal nitride layer, then this can be adjusted according to the desired electrical properties of the device. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art (MPEP 2144.05 (II)).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Lai et al. (US 20090039416 A1, hereinafter Lai).
Re: Claim 11, Lin discloses the semiconductor device of claim 1, wherein the gate dielectric layer (150, Lin) comprises aluminum (includes AlSiO in [0016], Lin).
Lin does not expressly disclose wherein the gate dielectric layer (150) comprises aluminum in an amount of less than 0.05 atomic%.
However, in the same semiconductor device field of endeavor, Lai discloses a gate dielectric layer (17 Al-doped silicon oxide in [0039], Fig. 1) comprises aluminum in an amount of 0.1 atomic% (layer 17 can be tuned to have a suitable dielectric constant wherein a very low atomic percent of aluminum results in a dielectric constant of 3.9 (silicon dioxide), wherein about 0.1 atomic percent reaches a dielectric constant of 4 in [0054]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Lai’s feature of a gate dielectric layer comprises aluminum in an amount of 0.1 atomic% to the Lin’s gate dielectric layer in order to have the predictable result of effectively tuning the dopant concentration of the aluminum in the gate dielectric layer to have a suitable dielectric constant ([0054], Lai).
Still, Lin modified by Lai does not explicitly disclose wherein the gate dielectric layer comprises aluminum in an amount of less than 0.05 atomic%, however, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the gate dielectric layer comprises aluminum in an amount of less than 0.05 atomic% because the concentration of aluminum can be controlled by the doping process and according to the desired electrical properties of the device. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. (MPEP 2144.05 (II)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Song (US 20190189767 A1) teaches “SEMICONDUCTOR DEVICES HAVING MULTI-THRESHOLD VOLTAGE”. This document is related to a semiconductor structure including a gate structure having a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer, and a gate metal layer.
Hsu (US 10249488 B1) teaches “SEMICONDUCTOR DEVICES WITH SAME CONDUCTIVE TYPE BUT DIFFERENT THRESHOLD VOLTAGES AND METHOD OF FABRICATING THE SAME”. This document is related to a semiconductor device including a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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