DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I, claims 1-9 and 11-21, in the reply filed on 12/3/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 8, 9, 11, 12, 14, 16, and 19 are rejected under 35 U.S.C. 102a1 as being anticipated by Jiang et al. (US 2014/0291843 A1).
Regarding claim 1, Jiang discloses:
A method of bonding a first component [package substrate (10); figures 1A-C] of a semiconductor package to a second component [PCB (18)] of the semiconductor package, comprising;
placing a composite material [hybrid solder ball (16)] on a first bonding pad [unshown connection pads; 0030] of the first component of the semiconductor package, wherein the composite material comprises a core structure comprising a first tin-containing alloy [SAC alloy; 0025] and a shell structure comprising a second tin-containing alloy [0029] having a different composition than the first tin-containing alloy [0025, 0028, 0029, 0044];
performing a first reflow process to melt the shell structure without melting the core structure, wherein the first reflow process bonds the composite material to the first bonding pad [0029, 0030, 0036, and figure 1A];
aligning the second component of the semiconductor package with the first component of the semiconductor package such that the composite material is in contact with a second bonding pad [pads (22)] of the second component [figure 1B]; and
performing a second reflow process to melt both the core structure and the shell structure to form a reflowed bonding material that bonds the first bonding pad and the second bonding pad [0033].
Regarding claim 2, Jiang discloses:
wherein the first tin-containing alloy comprises a tin-silver-copper alloy [SAC alloy; 0025] and the second tin-containing alloy comprises a tin-indium alloy [Sn-Ag-Bi-In; 0054].
Regarding claim 5, Jiang discloses:
wherein the first component of the semiconductor package comprises a package substrate [package substrate (10)] comprising a first side and a second side, at least one semiconductor die [die (12)] is mounted over the first side of the package substrate, and the first bonding pad is located on the second side of the package substrate [see figures 1A-C].
Regarding claim 8, Jiang discloses:
wherein the second component of the semiconductor package comprises a printed circuit board (PCB) [PCB (18)].
Regarding claims 9, 11, 12 and 16, Jiang discloses:
wherein the reflowed bonding material comprises a room temperature tensile strength in a range from approximately 80 MPa to approximately 100 MPa;
wherein the reflowed bonding material comprises intermetallic compounds formed as precipitates;
wherein the precipitates comprise one or more of Ag3Sn and Cu6Sn5;
wherein the reflowed bonding material comprises an alloy that is solid solution strengthened by a presence of indium that is dissolved within the reflowed bonding material, and
wherein the indium has a greater concentration near a surface of the reflowed bonding material relative to a concentration in an interior of the reflowed bonding material.
Note that while Jiang does not explicitly disclose the reflowed solder as having these properties, Jiang does disclose the claimed hybrid solder ball, an SAC core with a Sn-Bi alloy shell or Sn-In alloy shell, and heating within the claimed ranges to reflow the core.
Thus, it is the examiner’s position that the prior art process will achieve any claimed result since the prior art process, i.e. the process based on the prior art reference above, is identical to the claimed process. This reasoning applies to any claim in this action where a result is claimed.
Regarding claims 14 and 19, the limitations of these claims are addressed by the rejections of claims 1 and 2 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) as applied to claims 1 and 14 above.
Regarding claims 3 and 15, Jiang teaches:
performing the first reflow process at a first temperature that is in a first range from approximately 170° C to approximately 180° C [less than about 170/200°C; 0029]; and
performing the second reflow process at a second temperature that is in a second range from approximately 235°C to approximately 245°C [230-240°C; 0033].
Jiang and the claims differ in that Jiang does not teach the exact same ranges as recited in the instant claims.
However, one of ordinary skill in the art at the time/before the effective filing date of the invention would have considered the invention to have been obvious because the ranges taught by Jiang overlap the instantly claimed ranges and therefore are considered to establish a prima facie case of obviousness. It would have been obvious to one of ordinary skill in the art to select any portion of the disclosed ranges including the instantly claimed ranges from the ranges disclosed in the prior art reference, particularly in view of In re Peterson 65 USPQ2d 1379 (CAFC 2003); In re Geisler 43 USPQ2d 1365 (Fed. Cir. 1997); In re Woodruff, 16 USPQ2d 1934 (CCPA 1976); In re Malagari, 182 USPQ 549, 553 (CCPA 1974), and MPEP 2144.05. This reasoning applies to any claim and limitation in this action where a range is being claimed.
Regarding claim 13, Jiang teaches:
wherein the composite material becomes fully melted when subjected to a second reflow operation at a second reflow temperature that is in an a range from approximately 210°C to approximately 230°C [0033, 0037].
Jiang does not explicitly teach:
wherein the composite material becomes partially melted in response to being subjected to a temperature in a range from approximately 130°C to approximately 150°C,
Jiang does note that the alloy should be off-eutectic with a liquidus between 138-170°C; 0029.
Note that the applicant teaches eutectic Sn-Bi achieves this partial melting; PA Pub 0082.
The examiner notes that Sn-Bi solder alloys, including eutectic Sn-58Bi, with the claimed proportions are notoriously well-known since they can be readily bought from multiple suppliers.
One of ordinary skill in the art looking at Sn-Bi phase diagram would note that the Bi must be within the taught range in order to achieve the requirements set by Jiang. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Sn-58Bi since it meets the requirements of Jiang. In doing so, the partially melting requirement is met.
Claims 4, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) as applied to claims 2 and 19 above, and further in view of Saito et al. (US 2023/0173619 A1).
Regarding claims 4, 20, and 21, Jiang does not teach:
forming the shell structure to comprise a composition given by Snxlny,
wherein x is a first weight fraction having a value in a range from approximately 0.75 to approximately 0.85 and y is a second weight fraction having a value in a range from approximately 0.15 to approximately 0.25.
Note that Jiang is open to any low temperature solder (LTS), including ones that comprises Sn and In; 0054.
Saito teaches Sn-In soldering alloys may have melting points from 130-210°C, prefers 12-23 wt% In, and these solders avoid soft errors due to alpha-ray emission caused by Sn-Bi solders; 0006, 0010, and 0040-0044.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the Saito solders as the LTS in place of the a Sn-Bi solder in order to avoid the soft errors due to alpha-ray emission caused by Sn-Bi solders
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) as applied to claim 5 above, and further in view of Pan et al. (US 2019/0115269 A1).
Regarding claims 6 and 7, while Jiang does disclose a structure that meets claim 1, Pan is being applied to teach all the claimed components, thus Jiang does not teach semiconductor package comprising all of the following:
wherein the first component of the semiconductor package comprises a package substrate comprising a first side and a second side, at least one semiconductor die is mounted over the first side of the package substrate, and the first bonding pad is located on the second side of the package substrate;
wherein the semiconductor package further comprises an interposer mounted over the first side of the package substrate and a plurality of semiconductor dies mounted to the interposer;
wherein the semiconductor package further comprises a reinforcement structure mounted to the first side of the package substrate and laterally surrounding the interposer; and
wherein the second component of the semiconductor package comprises a printed circuit board (PCB).
Pan teaches a semiconductor package comprising dies (31, 32) with solder bumps (320), stiffener ring (40), interposer (20), and package substrate (10) wherein the stiffener ring and the bumped dies are mounted on interposer (20) which in turn is mounted on package substrate (10), wherein the semiconductor package is further mounted on a PCB, bumps (702, 802) can be encapsulated with underfill, and dies (31, 32) may be encapsulated with molding compound (60); 0056-0057, 0081 and figures 2, 17, and 24.
Note that Jiang is open to using the disclosed method to manufacture other electronic packages; 0031.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the method of Jiang to manufacture any desired semiconductor package, including that of Pan, minus any unexpected results.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) as applied to claim 14 above, and further in view of Hattori et al. (US 2015/0061129 A1).
Regarding claim 17, Jiang teaches:
wherein each of the core structures of the bonding structures has a diameter between 100 µm and 600 µm [SAC core is about 300 µm in diameter; 0044].
Jiang does not teach:
each of the shell structures of the bonding structures has a thickness that is between 15 µm and 40 µm.
However, Jiang does teach the particular size may be adapted to suit any particular implementation; 0044.
Hattori teaches a solder ball having a core and shell wherein the thickness of the shell is 100 µm or less and the core is 1-1000 µm and a specific example is 30 µm and 265 µm, respectively; 0044, 0046.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to manufacture the hybrid solder ball to sizes taught by Hattori because they are known sizes. Furthermore, one manufacturing the hybrid solder ball to the specific Hattori sizes would undoubtable achieve the claimed results since these sizes fall wholly within the claimed sizes. Furthermore, the size of the core is also dependent upon a particular implementation, so altering this size is nothing more than a routine step.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) as applied to claim 14 above, and further in view of Pan et al. (US 2019/0115269 A1) and Kim et al. (US 2022/0013445 A1).
Regarding claim 18, Jiang does not teach:
wherein mounting the semiconductor die over a first surface of a substrate comprises:
mounting a plurality of semiconductor dies to a first side of an interposer via a plurality of metal bump bonding structures;
forming a first underfill material portion between the plurality of semiconductor dies and the first surface of the interposer and laterally surrounding the metal bump bonding structures;
forming a molding portion laterally surrounding the plurality of semiconductor dies;
mounting the interposer to the first side of the substrate via a plurality of solder material portions between a second side of the interposer and the first side of the substrate; and
forming a second underfill material portion between the second side of the interposer and the first side of the substrate and laterally surrounding the plurality of solder material portions.
Concerning the plurality of dies, first underfill, and molding:
Pan teaches a semiconductor package comprising dies (31, 32) with solder bumps (320), stiffener ring (40), interposer (20), and package substrate (10) wherein the stiffener ring and the bumped dies are mounted on interposer (20) which in turn is mounted on package substrate (10), wherein the semiconductor package is further mounted on a PCB, bumps (702, 802) can be encapsulated with underfill, and dies (31, 32) may be encapsulated with molding compound (60); 0056-0057, 0081 and figures 2, 17, and 24.
Note that Jiang is open to using the disclosed method to manufacture other electronic packages; 0031.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the method of Jiang to manufacture any desired semiconductor package, including that of Pan, minus any unexpected results. Additionally, It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to encapsulate the bonding bumps (310, 320) with underfill in order to protect and improve the reliability of the bond. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to encapsulate the dies in figure 2 with molding to protect them and to strengthen the die interposer assembly.
Concerning the interposer underfill:
Kim teaches semiconductor package (500) comprising various components (450, 410, 120), interposer (100) and package (310), wherein the interposer is mounted to the package substrate via solder (183) and underfill (330); 0077, 0084 figure 9. Also note that the various components are also underfilled and encapsulated with a molding layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to also place underfill around the solder bonds between the interposer and package substrate, as taught by Kim, in order to protect and improve the reliability of the bond.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; see PTO 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS J GAMINO whose telephone number is (571)270-5826. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Keith Walker can be reached at 5712723458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CARLOS J GAMINO/Examiner, Art Unit 1735
/KEITH WALKER/Supervisory Patent Examiner, Art Unit 1735