DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
For the purposes of this examination, “binary tin-indium alloy” will be interpreted as an “alloy consisting of tin and indium”.
Claim Objections
Claim 21 is objected to because of the following informalities: in claim 21 “ally” should be “alloy”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the shell structure to comprise a composition given by Snxlny”. It is unclear if this composition is “the binary tin-indium alloy” of claim 1 or not. For the purposes of this examination, this limitation will be interpreted as being the same. Note that claim 20 has a similar indefiniteness and will also be interpreted in the same manner.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 21 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 21 recites, “the binary tin-indium ally comprises” which broadens “the binary tin-indium alloy” of claim 1 by opening it to other elements. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 8, 9, 11-16, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) in view of Saito et al. (US 2023/0173619 A1).
Regarding claim 1, Jiang teaches:
A method of bonding a first component [package substrate (10); figures 1A-C] of a semiconductor package to a second component [PCB (18)] of the semiconductor package, comprising;
placing a composite material [hybrid solder ball (16)] on a first bonding pad [unshown connection pads; 0030] of the first component of the semiconductor package, wherein the composite material comprises a core structure comprising a first tin-containing alloy [SAC alloy; 0025] and a shell structure comprising a second tin-containing alloy [0029, 0054] having a different composition than the first tin-containing alloy [0025, 0028, 0029, 0044];
performing a first reflow process to melt the shell structure without melting the core structure, wherein the shell structure contacts the first bonding pad [balls (16) contact the pads via the paste/flux] and wherein the first reflow process bonds the composite material to the first bonding pad [0029, 0030, 0036, and figure 1A];
aligning the second component of the semiconductor package with the first component of the semiconductor package such that the composite material is in contact with a second bonding pad [pads (22)] of the second component [figure 1B]; and
performing a second reflow process to melt both the core structure and the shell structure to form a reflowed bonding material that bonds the first bonding pad and the second bonding pad [0033].
Jiang does not teach:
the shell structure comprising a binary tin-indium alloy.
Note that Jiang is open to any low temperature solder (LTS), including ones that comprise Sn and In; 0054.
Saito teaches binary Sn-In soldering alloys may have melting points from 130-210°C, using 12-23 wt% In in order to be in the medium temperature range, and Sn-In solders avoid soft errors due to alpha-ray emission caused by Sn-Bi solders; 0006, 0010, 0013, and 0043.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use binary Sn-Al alloys taught by Saito as the LTS in place of the a Sn-Bi solder in order to avoid the soft errors due to alpha-ray emission caused by Sn-Bi solders. It also would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to tailor the alloy by controlling the amount of indium to 12-23wt% in order to arrive at a desired melting point, minus any unexpected results. Note that the examiner is not suggesting the use of the patented Sn-In-Ge alloy.
Regarding claim 2, Jiang teaches:
wherein the first tin-containing alloy comprises a tin-silver-copper alloy [SAC alloy; 0025].
Regarding claims 14 and 19, the limitations of these claims are addressed by the rejections of claims 1 and 2 above.
Regarding claims 3 and 15, Jiang teaches:
performing the first reflow process at a first temperature that is in a first range from approximately 170° C to approximately 180° C [less than about 170/200°C; 0029]; and
performing the second reflow process at a second temperature that is in a second range from approximately 235°C to approximately 245°C [230-240°C; 0033].
Jiang and the claims differ in that Jiang does not teach the exact same ranges as recited in the instant claims.
However, one of ordinary skill in the art at the time/before the effective filing date of the invention would have considered the invention to have been obvious because the ranges taught by Jiang overlap the instantly claimed ranges and therefore are considered to establish a prima facie case of obviousness. It would have been obvious to one of ordinary skill in the art to select any portion of the disclosed ranges including the instantly claimed ranges from the ranges disclosed in the prior art reference, particularly in view of In re Peterson 65 USPQ2d 1379 (CAFC 2003); In re Geisler 43 USPQ2d 1365 (Fed. Cir. 1997); In re Woodruff, 16 USPQ2d 1934 (CCPA 1976); In re Malagari, 182 USPQ 549, 553 (CCPA 1974), and MPEP 2144.05. This reasoning applies to any claim and limitation in this action where a range is being claimed.
Regarding claims 4, 20, and 21, Jiang does not teach:
forming/wherein the shell structure/binary tin-indium alloy to comprise a composition given by Snxlny,
wherein x is a first weight fraction having a value in a range from approximately 0.75 to approximately 0.85 and y is a second weight fraction having a value in a range from approximately 0.15 to approximately 0.25.
These claims are addressed in the rejection of claims 1, 14, and 19 above.
Regarding claim 5, Jiang teaches:
wherein the first component of the semiconductor package comprises a package substrate [package substrate (10)] comprising a first side and a second side, at least one semiconductor die [die (12)] is mounted over the first side of the package substrate, and the first bonding pad is located on the second side of the package substrate [see figures 1A-C].
Regarding claim 8, Jiang teaches:
wherein the second component of the semiconductor package comprises a printed circuit board (PCB) [PCB (18)].
Regarding claims 9, 11, 12 and 16, Jiang does not teach:
wherein the reflowed bonding material comprises a room temperature tensile strength in a range from approximately 80 MPa to approximately 100 MPa;
wherein the reflowed bonding material comprises intermetallic compounds formed as precipitates;
wherein the precipitates comprise one or more of Ag3Sn and Cu6Sn5;
wherein the reflowed bonding material comprises an alloy that is solid solution strengthened by a presence of indium that is dissolved within the reflowed bonding material, and
wherein the indium has a greater concentration near a surface of the reflowed bonding material relative to a concentration in an interior of the reflowed bonding material.
Concerning any claimed results:
However, since the prior art process, i.e. the process based on the combined prior art references above, is identical to the claimed process it is the examiner’s position that the prior art process will achieve any claimed result; such as these results. This reasoning applies to any claim in this action where a result is claimed.
Regarding claim 13, Jiang teaches:
wherein the composite material becomes fully melted when subjected to a second reflow operation at a second reflow temperature that is in an a range from approximately 210°C to approximately 230°C [0033, 0037].
Jiang does not explicitly teach:
wherein the composite material becomes partially melted in response to being subjected to a temperature in a range from approximately 130°C to approximately 150°C,
However, since the prior art composite material/shell structure is identical to that claimed then the prior art composite material/shell structure also achieves this. Note that Sn0.75-0.85In0.15-0.25 has an approximate mushy zone of 118-190°C; i.e. they inherently partially melt in this range.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) in view of Saito et al. (US 2023/0173619 A1) as applied to claim 5 above, and further in view of Pan et al. (US 2019/0115269 A1).
Regarding claims 6 and 7, while Jiang does disclose a structure that meets claim 1, Pan is being applied to teach all the claimed components, thus Jiang does not teach semiconductor package comprising all of the following:
wherein the first component of the semiconductor package comprises a package substrate comprising a first side and a second side, at least one semiconductor die is mounted over the first side of the package substrate, and the first bonding pad is located on the second side of the package substrate;
wherein the semiconductor package further comprises an interposer mounted over the first side of the package substrate and a plurality of semiconductor dies mounted to the interposer;
wherein the semiconductor package further comprises a reinforcement structure mounted to the first side of the package substrate and laterally surrounding the interposer; and
wherein the second component of the semiconductor package comprises a printed circuit board (PCB).
Pan teaches a semiconductor package comprising dies (31, 32) with solder bumps (320), stiffener ring (40), interposer (20), and package substrate (10) wherein the stiffener ring and the bumped dies are mounted on interposer (20) which in turn is mounted on package substrate (10), wherein the semiconductor package is further mounted on a PCB, bumps (702, 802) can be encapsulated with underfill, and dies (31, 32) may be encapsulated with molding compound (60); 0056-0057, 0081 and figures 2, 17, and 24.
Note that Jiang is open to using the disclosed method to manufacture other electronic packages; 0031.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the method of Jiang to manufacture any desired semiconductor package, including that of Pan, minus any unexpected results.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) in view of Saito et al. (US 2023/0173619 A1) as applied to claim 14 above, and further in view of Hattori et al. (US 2015/0061129 A1).
Regarding claim 17, Jiang teaches:
wherein each of the core structures of the bonding structures has a diameter between 100 µm and 600 µm [SAC core is about 300 µm in diameter; 0044].
Jiang does not teach:
each of the shell structures of the bonding structures has a thickness that is between 15 µm and 40 µm.
However, Jiang does teach the particular size may be adapted to suit any particular implementation; 0044.
Hattori teaches a solder ball having a core and shell wherein the thickness of the shell is 100 µm or less and the core is 1-1000 µm and a specific example is 30 µm and 265 µm, respectively; 0044, 0046.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to manufacture the hybrid solder ball to sizes taught by Hattori because they are known sizes. Furthermore, one manufacturing the hybrid solder ball to the specific Hattori sizes would undoubtable achieve the claimed results since these sizes fall wholly within the claimed sizes. Furthermore, the size of the core is also dependent upon a particular implementation, so altering this size is nothing more than a routine step.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2014/0291843 A1) in view of Saito et al. (US 2023/0173619 A1) as applied to claim 14 above, and further in view of Pan et al. (US 2019/0115269 A1) and Kim et al. (US 2022/0013445 A1).
Regarding claim 18, Jiang does not teach:
wherein mounting the semiconductor die over a first surface of a substrate comprises:
mounting a plurality of semiconductor dies to a first side of an interposer via a plurality of metal bump bonding structures;
forming a first underfill material portion between the plurality of semiconductor dies and the first surface of the interposer and laterally surrounding the metal bump bonding structures;
forming a molding portion laterally surrounding the plurality of semiconductor dies;
mounting the interposer to the first side of the substrate via a plurality of solder material portions between a second side of the interposer and the first side of the substrate; and
forming a second underfill material portion between the second side of the interposer and the first side of the substrate and laterally surrounding the plurality of solder material portions.
Concerning the plurality of dies, first underfill, and molding:
Pan teaches a semiconductor package comprising dies (31, 32) with solder bumps (320), stiffener ring (40), interposer (20), and package substrate (10) wherein the stiffener ring and the bumped dies are mounted on interposer (20) which in turn is mounted on package substrate (10), wherein the semiconductor package is further mounted on a PCB, bumps (702, 802) can be encapsulated with underfill, and dies (31, 32) may be encapsulated with molding compound (60); 0056-0057, 0081 and figures 2, 17, and 24.
Note that Jiang is open to using the disclosed method to manufacture other electronic packages; 0031.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the method of Jiang to manufacture any desired semiconductor package, including that of Pan, minus any unexpected results. Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to encapsulate the bonding bumps (310, 320) with underfill in order to protect and improve the reliability of the bond. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to encapsulate the dies in figure 2 with molding to protect them and to strengthen the die interposer assembly.
Concerning the interposer underfill:
Kim teaches semiconductor package (500) comprising various components (450, 410, 120), interposer (100) and package (310), wherein the interposer is mounted to the package substrate via solder (183) and underfill (330); 0077, 0084, and figure 9. Also note that the various components are also underfilled and encapsulated with a molding layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to also place underfill around the solder bonds between the interposer and package substrate, as taught by Kim, in order to protect and improve the reliability of the bond.
Response to Arguments
Applicant's arguments filed 4/20/26 have been fully considered but they are not persuasive.
The applicant states that the independent claims “are each amended to recite analogous elements that include a shell structure comprising a binary tin-indium alloy that directly contacts the respective bonding pad during the first reflow process.” Then later argues that “in Jiang's process, an intervening solder paste is disposed between the hybrid solder ball and the bond pad. The LTS coating (shell) of Jiang's hybrid solder ball does not contact the bond pad during attachment; rather, the solder paste intervenes between the shell and the pad.”
The examiner notes that the claims where not amended to recite “direct” contact and thus, Jiang teaches the shell structure contacts the pad via the paste/flux.
As for Jiang teaching the binary tin-indium alloy, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Even though Jiang does not teach using binary Sn-In alloy Jiang is open using other low melting point powders including other Sn-rich alloys; 0054.
The applicant argues,
“Saito teaches a solder alloy having "an alloy composition consisting of 12 to 23% by mass of In, and 0.001 to 0.08% by mass of Ge, with the balance being Sn and unavoidable impurities." Saito, paragraph [0051]. Saito's solder alloy is a Sn-In-Ge alloy containing germanium, not a binary tin-indium alloy. Saito further teaches that optional additive elements including Ag, Cu, Ni, and Co may be added. Id., paragraph [0051]. Accordingly, Saito does not cure the deficiencies of Jiang with respect to the binary tin-indium alloy element.
While Saito’s invention is drawn to a Sn-In-Ge alloy Saito still teaches binary Sn-In alloys and the effects of In. Thus, as noted in the rejection a selection of binary Sn-In is obvious, minus unexpected results.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS J GAMINO whose telephone number is (571)270-5826. The examiner can normally be reached M-F 9-6.
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/CARLOS J GAMINO/Examiner, Art Unit 1735
/KEITH WALKER/Supervisory Patent Examiner, Art Unit 1735
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