DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8,10-13 and 16-20 of U.S. Patent No. 12,112,829. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 are anticipated by claims 1-8,10-13 and 16-20 of the patent.
Regarding claim 21. Claim 1 or claim 11 of the patent recites a memory array circuit, comprising:
a plurality of first memory cells (claim 1, lines 3-4, a first set of memory cells) located in an inner area of a memory array;
a plurality of second memory cells (claim 1, lines 5-6) located along an edge of the memory array, wherein a first channel length of a first transistor in each of the plurality of first memory cells is less than a second channel length of a second transistor in each of the plurality of second memory cells (claim 1, lines 6-9); and
a plurality of dummy cells surrounding the memory array (claim 1, lines 10-13), wherein one of the plurality of dummy cells comprises:
one or more dummy active regions; and
a plurality of dummy gate structures over the one or more dummy active regions.
Regarding claim 22, claim 2 of the patent recites the memory array circuit of claim 21, wherein the number of the one or more dummy active regions within the one of the plurality of dummy cells is the same as or a multiple of the number of one or more active regions within one of the plurality of first memory cells or one of the plurality of second memory cells.
Regarding claim 23, claim 11 of the patent recites the memory array circuit of claim 21, wherein each of the one or more dummy active regions is formed extending in a first direction, and each of the plurality of dummy gate structures is formed extending in a second direction orthogonal to the first direction.
Regarding claim 24, claim 4 of the patent recites the memory array circuit of claim 21, wherein the memory array is a first memory array and the plurality of dummy cells are a plurality of first dummy cells, the memory array circuit further comprising:
a plurality of third memory cells located in an inner area of a second memory array;
a plurality of fourth memory cells located along an edge of the second memory array; and
a plurality of second dummy cells surrounding the second memory array.
Regarding claim 25, claim 5 of the patent recites the memory array circuit of claim 24, further comprising: a plurality of third dummy cells (the shared one or more cells) located between the edge of the second memory array and the edge of the first memory array.
Regarding claim 26, claim 6 of the patent recites the memory array circuit of claim 24, wherein a plurality of first bit lines of the first memory array are aligned with respect to a plurality of second bit lines of the second memory array.
Regarding claim 27, claim 7 of the patent recites the memory array circuit of claim 21, wherein each of the plurality of first memory cells and the plurality of second memory cells includes a predetermined number of transistors.
Regarding claim 28, claim 8 or claim 9 recites the memory array circuit of claim 27, wherein one of the plurality of first memory cells and the plurality of second memory cells is coupled to at least one of a power supply line, a word line, a negative control line or a select line of the memory array circuit by one or more corresponding transistors within the one of the plurality of first memory cells and the plurality of second memory cells.
Regarding claim 29, claim 10 of the patent recites the memory array circuit of claim 27, further comprising:
one or more first dummy transistors located between two adjacent ones of the plurality of first memory cells, wherein the one or more first dummy transistors are coupled to one or more of the first transistors within the two adjacent first memory cells; and one or more second dummy transistors located between two adjacent ones of the plurality of second memory cells, wherein the one or more second dummy transistors are coupled to one or more of the second transistors within the two adjacent second memory cells.
Regarding claim 30, claim 3 of the patent recites the memory array circuit of claim 21, wherein each of the plurality of dummy cells includes a plurality of dummy transistors.
Regarding claim 31, claim 11 or claim 1 of the patent recites a memory structure, comprising:
a plurality of memory cells forming a memory array, at least one of the plurality of memory cells comprising:
a plurality of active regions (claim 11, line 9); and
a plurality of gate structures disposed over the plurality of active regions (claim 11, lines 11-12), wherein a first channel length of a first transistor in a first set of the plurality of memory cells located in an inner area of the memory array is less than a second channel length of a second transistor in a second set of the plurality of memory cells located along an edge of the memory array (claim 11, lines 3-7); and
a plurality of dummy cells surrounding the memory array, wherein at least one of the dummy cells comprises one or more dummy active regions and a plurality of dummy gate structures disposed over the one or more dummy active regions (claim 11, lines 14-19).
Regarding claim 32, claim 12 of the patent recites the memory structure of claim 31, wherein the number of the one or more dummy active regions within one of the plurality of dummy cells is the same or a multiple of the number of the plurality of active regions within one of the plurality of memory cells.
Regarding claim 33, claim 13 of the patent recites the memory structure of claim 31, wherein at least one of the plurality of dummy cells or the plurality of memory cells further comprises one or more conductive layers having one or more conductive features.
Regarding claim 34, claim 11 of the patent recites the memory structure of claim 31, wherein each of the one or more dummy active regions is formed extending in a first direction, and each of the plurality of dummy gate structures is formed extending in a second direction orthogonal to the first direction.
Regarding claim 35, claims 1 and 4 recites the memory structure of claim 31, wherein the plurality of dummy cells are a plurality of first dummy cells, the memory array comprising:
a first sub-array comprising a third set of the plurality of memory cells located in an inner area of the first sub-array and a fourth set of the plurality of memory cells located along an edge of the first sub-array;
a second sub-array comprising a fifth set of the plurality of memory cells located in an inner area of the second sub-array and a sixth set of the plurality of memory cells located along an edge of the second sub-array; and
a plurality of second dummy cells located between the edge of the first sub-array and the edge of the second sub-array, and configured to separate the first sub-array and the second sub- array;
wherein the first set of the plurality of memory cells comprises the third set of the plurality of memory cells or the fifth set of the plurality of memory cells;
wherein the second set of the plurality of memory cells comprises the fourth set of the plurality of memory cells or the sixth set of the plurality of memory cells.
Regarding claim 36, claim 16 of the patent recites the memory structure of claim 35, wherein a plurality of first bit lines of the first sub-array are aligned with respect to a plurality of second bit lines of the second sub-array.
Regarding claim 37, claim 17 of the patent recites a method for fabricating a memory array circuit, the method comprising:
forming a plurality of first memory cells located in an inner area of a memory array (claim 16, lines 5-6);
forming a plurality of second memory cells along an edge of the memory array, wherein a first channel length of a first transistor in each of the plurality of first memory cells is less than a second channel length of a second transistor in each of the plurality of second memory cells (claim 16, lines 4-8); and
forming a plurality of dummy cells surrounding the memory array, by providing one or more dummy active regions and a plurality of dummy gate structures over the one or more dummy active regions (claim 16, lines 10-15).
Regarding claim 38. Claim 18 of the patent recites the method of claim 37, wherein the number of the one or more dummy active regions within one of the plurality of dummy cells is the same as or a multiple of the number of one or more active regions within one of the plurality of first memory cells or one of the plurality of second memory cells.
Regarding claim 39, claim 19 of the patent recites the method of claim 37, wherein forming the plurality of dummy cells comprises: forming each of the one or more dummy active regions extending in a first direction; and forming each of the plurality of dummy gate structures extending in a second direction orthogonal to the first direction.
Regarding claim 40, claim 20 of the patent recites the method of claim 37, wherein the memory array is a first memory array and the plurality of dummy cells are a first plurality of dummy cells, the method further comprising:
forming a plurality of third memory cells located in an inner area of a second memory array;
forming a plurality of fourth memory cells located along an edge of the second memory array;
forming a plurality of second dummy cells surrounding the second memory array; and
forming a plurality of third dummy cells located between the edge of the second memory array and the edge of the first memory array.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23, 27, 28, 31-34 and 37-9 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 2005/0044522 cited in the IDS filed on 07/30/2004) in view of Chou et al. (US 7,913,215, hereinafter “Chou”)
Regarding claims 21, 31 and 37. Maeda discloses a memory array circuit, a memory structure and a method for fabricating a memory array circuit, comprising:
a plurality of first memory cells (Fig. 1, A1, A1, A1) located in an inner area of a memory array;
a plurality of second memory cells (Fig. 1, A1, C1 …B5) located along an edge of the memory array; and
a plurality of dummy cells surrounding the memory array (Fig. 1, 20 and 30), wherein one of the plurality of dummy cells comprises:
one or more dummy active regions; and
a plurality of dummy gate structures over the one or more dummy active regions (paragraph [00253).
Maeda does not teach a first channel length of a first transistor in each of the plurality of first memory cells is less than a second channel length of a second transistor in each of the plurality of second memory cells. However, Chou discloses that a channel length of a transistor in the edge cell 208 can be larger than that of a transistor in the inner cell 206 to compensate variations induced by the manufacturing process and provide a larger storage node capacitance and a stronger driving current (column 3, lines 2-15). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a first channel length of a first transistor in the first set of memory cells is less than a second channel length of a second transistor in the second set of memory cells to compensate variations induced by the manufacturing process and provide a larger storage node capacitance and a stronger driving current in a memory device.
Regarding claims 22, 32 and 38, Maeda discloses the memory array circuit of claim 21, the memory structure of claim 31 and the method of claim 37, wherein the number of the one or more dummy active regions within the one of the plurality of dummy cells (Fig. 6, cell 20) is the same as or a multiple of the number of one or more active regions within one of the plurality of first memory cells (Fig. 3, cell 10) or one of the plurality of second memory cells.
Regarding claims 23, 34 and 39, Maeda (Fig. 15) shows the memory array circuit of claim 21, the memory structure of claim 31 and the method of claim 37, wherein each of the one or more dummy active regions (a1) is formed extending in a first direction, and each of the plurality of dummy gate structures (a2) is formed extending in a second direction orthogonal to the first direction.
Regarding claim 27, Maeda discloses the memory array circuit of claim 21, wherein each of the plurality of first memory cells and the plurality of second memory cells includes a predetermined number of transistors (Fig. 3).
Regarding claim 28, Maeda discloses the memory array circuit of claim 27, wherein one of the plurality of first memory cells and the plurality of second memory cells is coupled to at least one of a power supply line (Fig. 3, 114a), a word line, a negative control line or a select line of the memory array circuit by one or more corresponding transistors within the one of the plurality of first memory cells and the plurality of second memory cells.
Regarding claim 33, Maeda discloses the memory structure of claim 31, wherein at least one of the plurality of dummy cells or the plurality of memory cells further comprises one or more conductive layers (gate layers) having one or more conductive features.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Maeda in view of Chou as applied to claim 21 above, and further in view of Kuroda (US 2009/0116318).
The only difference between claim 30 and Maeda in view of chou is that each of the plurality of dummy cells includes a plurality of transistors. However, Kuroda discloses the use of a dummy cell including two or more transistors to eliminate an erroneous circuit operation and result in a faster operation (paragraph [0007] and [0060]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a dummy cell including two or more transistors to eliminate an erroneous circuit operation and result in a faster operation.
Conclusion
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/HUAN HOANG/Primary Examiner, Art Unit 2827