Prosecution Insights
Last updated: April 19, 2026
Application No. 18/789,714

VOLTAGE MONITOR AND OFF-CHIP DRIVER OF MEMORY DEVICE

Non-Final OA §112
Filed
Jul 31, 2024
Examiner
HIDALGO, FERNANDO N
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nanya Technology Corporation
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
95%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
1128 granted / 1209 resolved
+25.3% vs TC avg
Minimal +1% lift
Without
With
+1.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
18 currently pending
Career history
1227
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
35.7%
-4.3% vs TC avg
§102
18.3%
-21.7% vs TC avg
§112
23.8%
-16.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1209 resolved cases

Office Action

§112
DETAILED ACTION Examiner’s Note The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.” Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claim(s) 1-3 and 6-16 are allowed. The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, such as US 20200076429, US 9543954, US 20140002146, US 20070057692, DE 102004035273 A1, WO 9941836, US 5914898, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 1; expressing the claim(s) and highlighting subject matter, in brief and saliently: while the prior art generally teaches in a memory device an off-chip driver, said driver including pull-up and pull-down device around an output port, said prior art is silent on such teachings further including, in combination with the rest of the claim limitations, in whole, under MPEP 2103 as set forth above: a bridge switch, a first terminal of the bridge switch is coupled to the sensing node, a second terminal of the bridge switch is coupled to a connecting pad; an off-chip driver, comprising: a pull-up circuit, coupled between a high reference voltage and the connecting pad; and a pull-down circuit, coupled between the connecting pad and a low reference voltage; and a control circuit, coupled to the bridge switch and the off-chip driver, wherein in a test mode: the control circuit turns on the bridge switch, and the control circuit provides a bias voltage to the off-chip driver to let a first current value of a first leakage current flowing through the pull-up circuit match a second current value of a second leakage current flowing through the pull-down circuit. Or, similar claimed subject matter thereof, mutatis-mutandis. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim(s) 4 and 17 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for “wherein in the test mode, the control circuit turns on the control switch, turns off the pull-up switch and the pull-down switch,” does not reasonably provide enablement for “determines an absolute difference value between the first current value and the second current value according to according to the sensing signal on the connecting pad.” The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims. FIG. 4 seems relevant for the claimed invention. Claim 1, from which claim 4 depends, requires that 3340 turns on 320, in test mode. Claim 4 further requires that 340 turns on control switch SWCP and turns off MP and MN. Thus, as claimed, sensing signal SSEN is coupled through 320 to connecting pad DQPAD. Since MP and MN are off, no current on driver sourced from either VDDQ or VB can find its way to connecting pad DQPAD. In other words, DQPAD sees high impedance on 331 and high impedance on 332. Whatever current levels ILP through 331 and ILN through 332 may have are not stably measurable. As claimed, bridge switch 320 at its terminal directly electrically connected to DQPAD also see high impedance; any current that may source from the resistive network 310 through 320 is also not stably measurable. As claimed, it seems control circuit 340 is arranged to “determines” an absolute difference value between the first current value and the second current value. Currents ILP and ILN, whatever values they may have and whatever difference value between them there may exist, it is not one 340 is able to determine. There does not seem to be any feedback mechanism from ILP and ILN, or for that matter from DQPAD, that could find its way back to 340 for it to be able to “determine,” or ascertain value differences between ILP and ILN. At best 340 outputs signals VB and SC2 to driver 330, and even if PUPEN and PDNEN were also outputs from 340, none of these output signals from 340 can be used to collect information for 340 to “determine” current value difference between ILP and ILN. In regard to claim 17, FIG. 6 seems relevant for the claimed invention. Claim 17 claims, in part and relevantly: “wherein when the memory device is in a test mode, the control circuit turns off the control switch, and provides a bias voltage to the second terminal of the control switch to adjust a current flowing through the pull-down circuit.” Control switch SWCN, as claimed, is off. 443 provides a bias voltage VB to the second terminal of the control switch SWCN. Whatever value 443 may output on VB cannot “adjust” any current “flowing through the pull-down circuit” 432. MN at its terminal directly connected to SWCN see high impedance, ILN cannot flow through 432. Claim(s) 5 and 18 depend from claim(s) 4 and 17 and as such are also rejected for the same reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FERNANDO N. HIDALGO Primary Examiner Art Unit 2827 /Fernando Hidalgo/Primary Examiner, Art Unit 2827
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Prosecution Timeline

Jul 31, 2024
Application Filed
Feb 04, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
95%
With Interview (+1.4%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 1209 resolved cases by this examiner. Grant probability derived from career allow rate.

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