DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 07/31/2024, 11/11/2024, 05/25/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 07/31/2024. These drawings are review and accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Dwivedi et al (US 9,404,966 B2 hereinafter “Dwivedi”) in view of Gong et al (US 10,784,313 B1 hereinafter “Gong”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Dwivedi, for example in Figs. 1-12, discloses a semiconductor device (e.g., SELF-COMPENSATING DELAY CHAIN; in Fig. 3 related in Figs. 1-2, 4-12) comprising:
an array of M inverters (e.g., inverter 50, 52, 54, 56; in Fig. 3 related in Figs. 1-2, 4-12), M being an integer of at least 2 such that the array of M inverters includes at least a first inverter and a second inverter (e.g., inverter 50, 52; in Fig. 3 related in Figs. 1-2, 4-12);
(M-1) pairs of Dynamic Random Access Memory (DRAM) coupled to the array of M inverters (i.e., DRAM cell having elements 60 and 65; in Fig. 3 related in Figs. 1-2, 4-12), wherein: (M-1) inverters of the array of M inverters are each connected in parallel with a pair of DRAMs of the (M-1) pairs of DRAMs (see for example in Fig. 3 related in Figs. 1-2, 4-12).
However, Dwivedi is silent with regard to (M-1) pairs of resistive memory devices (RMDs) coupled to the array of M inverters; and a write line coupled to an input of the first inverter.
In the same field of endeavor, Gong, for example in Figs. 1-9, discloses (M-1) pairs of resistive memory devices (RMDs) coupled to the array of M inverters (e.g., PCM/RRAM; in Fig. 1 related in Figs. 2-9); and a write line (e.g., WL 12; in Fig. 1 related in Figs. 2-9) coupled to an input of the first inverter (e.g., inverter 50; in Fig. 1 related in Figs. 2-9).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Dwivedi such as performance characteristic monitoring circuit and method (see for example in Figs. 1-12 of Dwivedi) by incorporating the teaching of Gong such as integrated resistive processing unit to avoid abrupt set of RRAM and abrupt reset of PCM (see for example in Figs. 1-9 of Gong). In order to provide a memory structure having multiple of inverter devices and resistive memory are connected in parallel (see for example in Fig. 1 related in Figs. 2-9 of Gong).
Regarding claim 2, the above Dwivedi/Gong, combination discloses wherein: the second inverter (e.g., inverter 52; in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above) has an input coupled to an output of the first inverter (e.g., inverter 50; in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above), a first pair of RMDs of the (M-1) pairs of RMDs is coupled in parallel with the second inverter, the first pair of RMDs includes a first RMD and a second RMD, the first RMD is coupled between the input of the second inverter and an output node, and the second RMD is coupled between an output of the second inverter and the output node (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 3, the above Dwivedi/Gong, combination discloses wherein: the (M-1) pairs of RMDs are controllable whereby the array of M inverters and the (M-1) pairs of RMDs are configured to be controllably programmed as each of a NOT gate and a YES gate (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 4, the above Dwivedi/Gong, combination discloses wherein: the (M-1) pairs of RMDs have commonly-coupled output nodes (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 5, the above Dwivedi/Gong, combination discloses wherein: the commonly-coupled output nodes are configured to carry an output signal of each of the NOT gate and the YES gate (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 6, the above Dwinvedi/Gong, combination discloses wherein: the array of M inverters and the (M-1) pairs of RMDs are configured to perform a physically unclonable function (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above), and in a randomized programming operation of a first pair of RMDs of the (M-1) pairs of RMDs (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above), the semiconductor device is configured to apply a first voltage to the write line while floating a common output node of the first pair of RMDs (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
The structure in of the prior art (Dwivedi/Gong) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114 (II).
Regarding claim 7, the above Dwivedi/Gong, combination discloses wherein: in a read operation of the first pair of RMDs, the semiconductor device is configured to apply a second voltage to the write line and output a measurement voltage from the common output node (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above). Also, the structure in of the prior art (Dwivedi/Gong) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114 (II).
Regarding Independent Claim 8, Dwivedi, for example in Figs. 1-12, discloses a semiconductor device (e.g., SELF-COMPENSATING DELAY CHAIN; in Fig. 3 related in Figs. 1-2, 4-12), comprising:
M inverters, M being a positive integer, the M inverters being electrically connected serially (e.g., inverter 50, 52, 54, 56; in Fig. 3 related in Figs. 1-2, 4-12); and
(M-1) pairs of Dynamic Random Access Memory (DRAMs) (i.e., DRAM cell having elements 60 and 65; in Fig. 3 related in Figs. 1-2, 4-12),
wherein:
a first inverter of the M inverters is electrically connected to a first node, the first node being electrically connected to a first DRAM of a first pair of DRAMs of the (M-1) pairs of DRAMs and to a second inverter of the M inverters (see for example in Fig. 3 related in Figs. 1-2, 4-12), and
each inverter after the first inverter of the M inverters is electrically connected in parallel with a pair of DRAMs of the (M-1) pairs of DRAMs (see for example in Fig. 3 related in Figs. 1-2, 4-12).
However, Dwivedi is silent with regard to (M-1) pairs of resistive memory devices (RMDs) coupled to the array of M inverters.
In the same field of endeavor, Gong, for example in Figs. 1-9, discloses (M-1) pairs of resistive memory devices (RMDs) coupled to the array of M inverters (e.g., PCM/RRAM; in Fig. 1 related in Figs. 2-9).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Dwivedi such as performance characteristic monitoring circuit and method (see for example in Figs. 1-12 of Dwivedi) by incorporating the teaching of Gong such as integrated resistive processing unit to avoid abrupt set of RRAM and abrupt reset of PCM (see for example in Figs. 1-9 of Gong). In order to provide a memory structure having multiple of inverter devices and resistive memory are connected in parallel (see for example in Fig. 1 related in Figs. 2-9 of Gong).
Regarding claim 9, the above Dwivedi/Gong, combination discloses further comprising: a write line configured to program one or more RMDs of the (M-1) pairs of RMDs, the write line being electrically connected to an input of the first inverter of the M inverters (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 10, the above Dwivedi/Gong, combination discloses further comprising: a plurality of output nodes, wherein each output node electrically connects the RMDs of a corresponding pair of the (M-1) pairs of RMDs to one another (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 11, the above Dwinvedi/Gong, combination discloses wherein: a first RMD of a corresponding pair of RMDs is electrically connected to a first inverter output, a second inverter input, and a first output node of the plurality of output nodes (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Regarding claim 12, the above Dwivedi/Gong, combination discloses wherein: a second RMD of the corresponding pair of RMDs is electrically connected to a second inverter output, a third inverter input, and the first output node of the plurality of output nodes (see for example in Fig. 3 related in Figs. 1-2, 4-12 of Dwivedi and also see in Fig. 1 related in Figs. 2-9 of Gong, as discussed above).
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior arts of record fail to teach or suggest a semiconductor device as recited in claim13, and particularly, further comprising: a first level of the semiconductor device including the M inverters being first M inverters of a plurality of M inverters and the (M-1) pairs of RMDs being first (M-1) pairs of RMDs of a plurality of (M-1) pairs of RMDs; and a second level of the semiconductor device above the first level of the semiconductor device, the second level of the semiconductor device including: second M inverters of the plurality of M inverters, the second M inverters being electrically connected serially; and second (M-1) pairs of RMDs of the plurality of (M-1) pairs of RMDs, the second (M-1) pairs of RMDs being electrically connected in parallel with the second M inverters except for a first inverter of the second M inverters, wherein an input of the first inverter of the second M inverters is electrically connected to an output node of a corresponding pair of RMDs of the first (M-1) pairs of RMDs.
Regarding claim 14, the prior arts of record fail to teach or suggest a semiconductor device as recited in claim14, and particularly, wherein: the M inverters are first M inverters of a plurality of M inverters, the (M-1) pairs of RMDs are first (M-1) pairs of RMDs of a plurality of (M-1) pairs of RMDs, and the semiconductor device further comprises: second M inverters of the plurality of M inverters, the second M inverters being parallel to the first M inverters; and second (M-1) pairs of RMDs of the plurality of (M-1) pairs of RMDs, the second (M-1) pairs of RMDs being electrically connected in parallel with the second M inverters except for a first inverter of the second M inverters, wherein an input of the first inverter of the second M inverters is electrically connected to an output node of a pair of RMDs of the first (M-1) pairs of RMDs.
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations. Dwivedi et al (US 9,404,966 B2 hereinafter “Dwivedi”) and Gong et al (US 10,784,313 B1 hereinafter “Gong”), taken individually or in combination, do not teach the claimed invention having the following limitations, in combination with the remaining claimed limitations:
Per claim 15, there is no teaching, suggestion, or motivation for combination in the prior art to the steps of setting a first resistive memory device (RMD) of a pair of RMDs in a first programming operation; setting a second RMD of the pair of RMDs in a second programming operation; randomly resetting one of the first or second RMDs in a third programming operation; and performing a read operation on the pair of RMDs.
Conclusion
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/THA-O H BUI/ Primary Examiner, Art Unit 2825 01/10/2026