DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 4-9 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (U.S. Publication No. 2020/0328188 A1; hereinafter Liu)
With respect to claim 4, Liu discloses a method of making a semiconductor device, the method comprising: forming a first device [504 or 502] on a first side of a substrate [522,526], wherein the first device comprises a first source/drain (S/D) electrode (see Figure 5A; S/D of [532] or [510]); forming a second device [502 or 504] (opposite of the first device) on a second side of the substrate, wherein the second side of the substrate is opposite the first side of the substrate, and the second device comprises a second S/D electrode (S/D of [532] or [510]; opposite of first s/d electrode); and forming a through substrate via (TSV) [528/524] (see Figure 5A) electrically connecting the first S/D electrode to the second S/D electrode, wherein a width of the TSV is equal to a width of at least one of the first S/D electrode or the second S/D electrode (See Figure 5A; right side; depending on orientation based on the language of the claim, [502] can be considered the first device or [504] can be considered the first device).
With respect to claim 5, Liu discloses forming a conductive line [553 or 554] on the second side of the substrate, wherein the conductive line is farther from the substrate than the second S/D electrode (see Figure 5A or 5B).
With respect to claim 6, Liu discloses forming a jump via electrically connecting the first S/D electrode to the conductive line, wherein an entirety of the jump via is separated from the second S/D electrode (See Figure 5A or 5B).
With respect to claim 7, Liu discloses wherein forming the jump via comprises forming the jump via extending through the substrate (See Figure 5A or 5B).
With respect to claim 8, Liu discloses forming a via electrically connecting the conductive line to the second S/D electrode, wherein the second S/D electrode is electrically between the first S/D electrode and the conductive line (See Figure 5B).
With respect to claim 9, Liu discloses wherein a width of the first S/D electrode is greater than a width of the second S/D electrode (See Figure 5A; when [502] is considered the first device, the first S/D electrode is greater than the width of the second S/D electrode).
With respect to claim 12, Liu discloses wherein forming the TSV comprises forming the TSV after forming the first device or the second device (See Figures 6A-7B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Peng et al. (U.S. Publication No. 2020/0104447 A1; hereinafter Peng)
With respect to claim 1, Liu discloses a method of making a semiconductor device, the method comprising: forming a first device [504] on a first side of a substrate [522,526], wherein the first device comprises a first source/drain (S/D) electrode (see Figure 5A; source/drain electrodes of [538]); forming a second device [502] on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate, and the second device comprises a gate electrode [518]; forming a through substrate via (TSV) [528/524] (see Figure 5A) wherein the TSV electrically connects the first S/D electrode and the gate electrode (See Figure 5A; right side). Liu fails to disclose forming a through substrate via (TSV) at a location determined using an automatic placement and routing (APR) tool. In the same field of endeavor, Peng teaches forming a through substrate via (TSV) at a location determined using an automatic placement and routing (APR) tool (See Figure 2C-2D, 6D, 7 and ¶[0143]). Implementation of an APR tool for the placement of the TSV of Liu, as taught by Peng allows for quick information on the orientation and placement of cells and vias based on the libraries of standard cells and design rules to provide quick and efficient processing of design layouts (See Peng ¶[0159]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Liu and Peng discloses wherein forming the TSV comprises forming the TSV satisfying design rules for the first side of the substrate and design rules for the second side of the substrate (see Liu Figure 5A and Peng Figure 6D, ¶[0159]).
With respect to claim 3, the combination of Liu and Peng discloses wherein forming the first device comprises forming a first inverter, and forming the second device comprises forming a second inverter (See Peng Figures 2C-2D and ¶[0052]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Choi et al. (U.S. Publication No. 2021/0305429 A1; hereinafter Choi).
With respect to claim 10, Liu fails to disclose wherein forming the first device comprises forming a gate all around (GAA) transistor.
In the same field of endeavor, Choi teaches wherein forming the first device comprises forming a gate all around (GAA) transistor (See ¶[0021]). Implementation of a GAA transistor within the device of Liu as taught by Choi alls for multiple types of transistors to be utilized in a multiple parallel channel structure with multiple active devices within a single device (see ¶[0055]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu
With respect to claim 11, Liu fails to disclose wherein forming the TSV comprises forming the TSV prior to forming the first device and the second device. However, it has been held that selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). Therefore, it would have been appreciated by one of ordinary skill in the art at the time of invention that the order of steps to produce the TSV after forming the first device or the second device (see Figures 6A-7B) would produce a functionally identical device to that of forming the TSV prior to forming the first device and the second device.
Allowable Subject Matter
Claims 13-20 are allowed.
With respect to claims 13-20, none of the prior art teaches or suggests, alone or in combination, a method of making a semiconductor device, the method comprising: each of the plurality of second devices has a second threshold voltage and a second pitch between adjacent gate structure of the plurality of second devices, and the second side of the substrate is free of devices having the first threshold voltage and the first pitch, wherein at least one of the following conditions is satisfied: the first threshold voltage is different from the second threshold voltage; or the first pitch is different from the second pitch.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (U.S. Publication No. 2020/0104462 A1) discloses APR layout systems but fails to disclose a method of making a semiconductor device, the method comprising: each of the plurality of second devices has a second threshold voltage and a second pitch between adjacent gate structure of the plurality of second devices, and the second side of the substrate is free of devices having the first threshold voltage and the first pitch, wherein at least one of the following conditions is satisfied: the first threshold voltage is different from the second threshold voltage; or the first pitch is different from the second pitch.
Lin (U.S. Publication No. 2015/0021789 A1) discloses a bonded device but fails to disclose a method of making a semiconductor device, the method comprising: each of the plurality of second devices has a second threshold voltage and a second pitch between adjacent gate structure of the plurality of second devices, and the second side of the substrate is free of devices having the first threshold voltage and the first pitch, wherein at least one of the following conditions is satisfied: the first threshold voltage is different from the second threshold voltage; or the first pitch is different from the second pitch.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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