DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/25/2025 and 07/31/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8 and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (PG Pub 2018/0301389; hereinafter Liu).
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Regarding claim 1, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches a semiconductor device comprising:
an encapsulant 210 with a first side (annotated “s1”) and a second side (annotated “s2”) opposite the first side (see Fig.12), the first side being curved as the first side intersects a semiconductor die (annotated “die”; see Fig. 12), the second side being straight as the second side intersects a through via (CP) extending through the encapsulant (see Fig. 12);
an underfill material 160 extending from the encapsulant to a package 240 electrically connected to the through via (through 150); and
an interface material 150 extending through the underfill material (see Fig. 12).
Regarding claim 2, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the underfill material 160 is in physical contact with the first side (“s1”) (see Fig.12).
Regarding claim 4, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the interface material 150 is discontinuous (see Fig. 12).
Regarding claim 5, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the interface material 150 has sidewalls that are coterminus (sharing the same area) with the semiconductor die (”die”) (see Fig. 12).
Regarding claim 6, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the package 240 is in physical contact (through 220) with the interface material 150 (see Fig.12).
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Regarding claim 8, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches a semiconductor device comprising:
a first redistribution layer 220;
a first encapsulant 210 over the first redistribution layer (see Fig. 12);
a first semiconductor die (annotated “die”) located within the first encapsulant (see Fig. 12), the first encapsulant having at least one curved surface (annotated “s1”) adjacent to the first semiconductor die (see Fig.1 2);
a through via (CP) extending through the first encapsulant (see Fig. 12);
a first package 300 electrically connected to the through via (through 250); and
an interface material 250 extending through an underfill material (IN) between the first package and the first semiconductor die (see Fig. 12).
Regarding claim 9, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches
the first semiconductor die (“die”) has a first width (“w1”) and the interface material (IN) has a second width (“w2”) larger than the first width (see Fig.12).
Regarding claim 10, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the first semiconductor die (“die”) has a first width (“w1”) and the interface material (IN) has a second width (“w3”) less than the first width (see Fig. 12).
Regarding claim 11, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the first semiconductor die (“die”) has a first width (“w1”) and the interface material (IN) has the first width (see Fig.12).
Regarding claim 12, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches at least a portion of a sidewall of the through via is exposed by the encapsulant.
Regarding claim 13, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the first semiconductor die (“die”) has a first height (vertical portion enclosed in box) and the encapsulant 210 has a second height (vertical height is portion between 220 and IN) larger than the first height (see Fig. 12).
2. Claim(s) 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (PG Pub 2019/0027446; hereinafter Cheng).
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Regarding claim 15, refer to Fig. 18 provided above, Cheng teaches a semiconductor device comprising:
a package 300 electrically connected to through vias (TV) through external connections 310, the external connections extending through an underfill 400;
a semiconductor die 200 located between the through vias (see Fig.18), wherein an interface material extends (DAF) from the semiconductor die to the package (see Fig. 18); and
a material 210 extending away from the semiconductor die along a curved line (see Fig. 18).
Regarding claim 16, refer to Fig. 18 provided above, Cheng teaches the interface material (DAF) is in physical contact with the curved line (see Fig. 18).
Regarding claim 17, refer to Fig. 18 provided above, Cheng teaches the underfill 400 is in physical contact with the curved line (see Fig.18).
Regarding claim 18, refer to Fig. 18 provided above, Cheng teaches the interface material 400 is discontinuous (broken by 310) (see Fig.18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to claim 6 above, and further in view of Cheng et al. (PG Pub 2019/0027446; hereinafter Cheng).
Regarding claim 7, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches a package, Lee does not teach the package comprises: a substrate; a first semiconductor die; and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are connected to the substrate through wire bonds.
In the same field of endeavor, refer to Fig. 18-provided above, Cheng teaches a package structure comprising: a package 300, wherein the package comprises a substrate (“sub”); a first semiconductor die (“die-1”); and a second semiconductor die (“die-2”), wherein the first semiconductor die and the second semiconductor die are connected to the substrate through wire bonds (“wire”).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the package of Liu with the dial component package of Cheng, to create a more robust package.
Regarding claim 14, refer to the examiner’s mark-up of Fig. 12 provided above, Liu teaches the through via (CP) has a third height (vertical height) equal to the second height (height of encap). Liu does not teach the third height larger than the second height.
In the same field of endeavor, refer to Fig. 18-provided above, Cheng teaches a package structure comprising: a first semiconductor die 200 has a first height (“h1”); an encapsulant 210 has a second height (“h2”) larger than the first height (see Fig. 18); and a through via (TV) has a third height (“h3”) larger than the second height (see Fig. 18).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the height of the through via to be larger than the height of the encapsulant, as taught by Cheng, since a change in shape are considered routine expedients that do not change the functionality of the through via.
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, as applied to claim 15 above, and further in view of Yu et al. (PG Pub 2021/0066279; hereinafter Yu).
Regarding claim 19 and claim 20, refer to Fig. 18 provided above, Cheng teaches the interface material (DAF). Cheng does not teach: (Regarding claim 19) the interface material “has a thermal conductivity of between about 15 W/k*m and about 20 W/K*m”; and (Regarding claim 20), the interface material has “a stiffness of between about 250 N/mm and about 2500 N/mm”.
In the same field of endeavor, Yu teaches a die attach film (DAF) having high thermal conductivity, a polymer-based layer, a graphite film and a solder layer; which is the same material composition as the Applicants (see Applicants spec … “interface material 127 is a material such as lead-tin based solder (PbSn), lead-free solder, indium, carbon composite materials, graphite, carbon nanotubes, or other suitable thermally conductive materials.”). Since Cheng is using the same material DAF material composition, inherent material properties such as thermal conductivity (between about 15 W/k*m and about 20 W/K*m) and stiffness (between about 250 N/mm and about 2500 N/mm.) would be inherent taught.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Graphite, as taught by Cheng, for the purpose of choosing a suitable and well-known DAF material composition.
Allowable Subject Matter
5. Claim 3 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 3, teaches the interface material is in physical contact with the first side.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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