DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-4 are rejected under 35 U.S.C. 103 as obvious over Avsian et al. (US 2011/0248410 A1), hereinafter as A1, in view of Noma et al. (US 2008/0093708 A1), hereinafter as N1
4. Regarding Claim 1, A1 discloses a method (see in particular Figs. 2A-7, 11) comprising:
forming a chip stack (elements 12, 12A, see [0061] “Individual microelectronic elements 12 are referred to as the known good die”; also see [0056] “Each microelectronic element of the uncut wafer 10 has a device region 26 (area within dashed lines 27 (FIG. 1A) and within solid lines 27 (FIG. 1B)) in which active semiconductor devices and typically also passive devices are disposed”, [0101] “semiconductor die or microelectronic elements”) comprising a first semiconductor chip (bottom element 12) and a second semiconductor chip (element 12A), the first semiconductor chip comprising a first semiconductor substrate (the semiconductor substrate of the semiconductor die of element 12) and a first interconnect structure (element 24, see [0065] “traces 24”), and the second semiconductor chip comprising a second semiconductor substrate (semiconductor substrate of the semiconductor die of element 12A) and a second interconnect structure (element 24A);
cutting through the chip stack from a first side of the chip stack (see Fig. 6A top side and see [0046]), the cutting forming angled sidewalls on at least one of the first interconnect structure or the second interconnect structure (see Fig. 6A);
singulating the chip stack from a larger substrate (see Figs. 5-7 the larger substrate contains additional chip stacks which are singulated from each other); and
bonding the singulated chip stack to a third semiconductor structure (see Fig. 11 [0080] “One or more additional microelectronic elements 70 can be attached to a rear face 88 of the package 80”).
A1 does not explicitly disclose the cutting is etching
N1 discloses the cutting is etching (see Figs. 1-5A and [0043] “portions of the first wirings 3 are exposed by etching the second insulation film 6 and the first insulation film 2 using the photoresist film (not shown) as a mask”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of N1 with A1 because the combination allows for reduced cracks and separation in the semiconductor device and allows for a desired shape groove to be formed at a scribing line (see [0037, 0047]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming a cut at a scribing line for another in a similar device to obtain predictable results (see N1 Figs. 1-5A and [0038]).
5. Regarding Claim 2, A1, N1 disclose the method of claim 1, wherein the etching comprises etching through the first semiconductor substrate at a first rate and etching through the first interconnect structure at a second rate slower than the first rate (see Fig. 4A-5A and [0043] “Then portions of the first wirings 3 are exposed by etching the second insulation film 6 and the first insulation film 2 using the photoresist film (not shown) as a mask” The etch exposes and stops at the wiring material element 3, lower etch rate, after removing the insulating material, higher etch rate).
6. Regarding Claim 3, A1, N1 disclose the method of claim 1, wherein the angled sidewalls form an interior angle of less than 90 degrees with respect to a bonding interface between the first semiconductor chip and the second semiconductor chip (see A1 Fig. 11 the bonding interface is lateral and the angle sidewalls are angled such as to be less than 90 degrees).
7. Regarding Claim 4, A1, N1 disclose the method of claim 1, further comprising thinning the first semiconductor substrate before the etching (see N1 [0033] “Thickness of the semiconductor substrate 1 is reduced by back-grinding a surface of the semiconductor substrate 1”).
8. Claims 5-6 are rejected under 35 U.S.C. 103 as obvious over Avsian et al. (US 2011/0248410 A1), hereinafter as A1, in view of Noma et al. (US 2008/0093708 A1), hereinafter as N1, in view of Thacker et al. (US 2013/0320567 A1), hereinafter as T1
9. Regarding Claim 5, A1, N1 disclose the method of claim 1, further comprising forming interlevel interconnects (see A1 Figs. 6A-8 elements 66,75,166, and see [0072-0073, 0076] “leads 66”) on the first semiconductor substrate after the singulating and before the bonding (see A1 Figs. 6-8, [0072-0073, 0076]).
A1, N1 do not disclose forming through vias.
T1 discloses forming through vias and redistribution layer(s) (see Figs. 3-6 elements 122, see [0055] “TSVs 122 … other TSVs and planar redistribution layers on surfaces 112 and/or sides 114 may be designed and fabricated as needed for distribution of signal, power and ground”).
The through vias and redistribution layer as taught by T1 are incorporated as through vias and redistribution layer of A1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with A1 because the combination allows for distribution of signal, power, and ground (see T1 [0055]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known conductive interconnect between stacked layers for another in a similar device to obtain predictable results (see T1 [0055] “other TSVs and planar redistribution layers on surfaces 112 and/or sides 114 may be designed and fabricated as needed for distribution of signal, power and ground”).
10. Regarding Claim 6, A1, N1, T1 disclose the method of claim 5, further comprising forming a redistribution layer over the first side of the chip stack, wherein the redistribution layer is electrically coupled to the through vias (see T1 see [0055] “TSVs 122 … other TSVs and planar redistribution layers on surfaces 112 and/or sides 114 may be designed and fabricated as needed for distribution of signal, power and ground”).
11. Claim 7 is rejected under 35 U.S.C. 103 as obvious over Avsian et al. (US 2011/0248410 A1), hereinafter as A1, in view of Noma et al. (US 2008/0093708 A1), hereinafter as N1, in view of Kitagawa (WO 2015045422 A1), hereinafter as K1
12. Regarding Claim 7, A1, N1 disclose the method of claim 1.
A1, N1 do not disclose wherein the third semiconductor structure is an unsingulated semiconductor wafer.
K1 discloses wherein the third semiconductor structure is an unsingulated semiconductor wafer (see Figs. 2(a)-(d) and pg. 7 “The semiconductor mounting structure 1 includes a semiconductor wafer substrate 2 having a plurality of element mounting regions 24, a plurality of semiconductor bare chips 3” The semiconductor chips can be further mounted on an unsingulated semiconductor wafer and subsequently packaged and singulated).
The additional packaging step with the unsingulated semiconductor wafer as taught by K1 is incorporated as an additional packaging step with an unsingulated semiconductor wafer of A1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with A1 because the combination provides added mechanical and electrical protection by mounting and sealing the chip and improve connection reliability (see K1 pg. 7); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one stacked package component for another in a similar device to obtain predictable results (see K1 pg. 7 and A1 [0080] various types of combinations of electronic components and packaging subsequent to the singulation is possible).
13. Claims 8, 13 are rejected under 35 U.S.C. 103 as obvious over Thacker et al. (US 2013/0320567 A1), hereinafter as T1, in view of Kim et al. (US 2013/0069239 A1), hereinafter as K1, in view of Oh (US 2009/0321954 A1), hereinafter as O1
14. Regarding Claim 8, T1 disclose a method (see Figs. 1-8B) comprising:
singulating a first chip (first one of the elements “CHIP”) from a first wafer (see Fig. 1 and [0033] “chips on a wafer”), the first chip comprising a first semiconductor substrate (see [0032] “wafer-level fabrication of semiconductor components, several chips are fabricated on a single wafer. Each chip (or die) on the wafer is separated from its neighbors by a small area of silicon called the dicing lane or saw lane”);
bonding the first chip to a second chip (see Fig. 4, 8A-B second element “CHIP” on which the first chip is stacked, see [0050] “First, layer 1 and layer 2 wafers, each with pits/trenches etched along the dicing lanes, may be stacked using the process shown in FIG. 4”) on a second wafer (see [0050]);
forming through vias (see Figs. 8A-B elements TSV, [0050] “These TSVs may be fabricated by etching high-aspect ratio blind vias in a silicon substrate and filling them with a conductive material, such as copper. After this operation, the wafers may be thinned from the backside to `reveal` the TSVs. Note t”) through the first semiconductor substrate of the first chip to the second chip (see Figs. 8A-B).
T1 does not appear to explicitly disclose encapsulating the first chip with a dielectric material; forming a multi-layer interconnect structure over the first chip and the dielectric material, wherein the multi-layer interconnect structure comprises a plurality of dielectric layers and a plurality of conductive layers, and wherein the through vias are electrically coupled to the multi-layer interconnect structure; and forming external contacts on the multi-layer interconnect structure.
K1 discloses (see Figs. 15a-j) encapsulating the first chip (element 558, see [0148] “semiconductor die 558”) with a dielectric material (element 580, see [0151] “MUF material 580 can be an encapsulant”); forming a multi-layer interconnect structure (see Fig. 15i element 606, see [0154] “TSV interposer or substrate 606”) over the first chip and the dielectric material (see Fig. 15i), wherein the multi-layer interconnect structure comprises a plurality of dielectric layers and a plurality of conductive layers (see Fig. 15i at least three layers), and wherein the through vias are electrically coupled to the multi-layer interconnect structure (see Fig. 15i connected through element 566, 564 to element 558).
The stacked structure with encapsulation and multi-layer interconnect as taught by K1 is incorporated as a stacked structure with encapsulation and multi-layer interconnect of T1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with T1 because the combination allows for compact and improved electrical connection among the conductive components and stacked chips, and multiple interconnect structures for connecting between a top and bottom surface of the package with the stacked die (see K1 Figs. 15a-j [0144, 0155]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known stacked die packaging for another in a similar device to obtain predictable results (see K1 Figs. 15a-j).
T1, K1 do not explicitly disclose forming external contacts on the multi-layer interconnect structure
O1 discloses forming external contacts on the multi-layer interconnect structure (see Fig. 9 solder bump elements 651, 650 for external contacts to the chip stack can be provided on both the top and the bottom side surfaces, see [0151] “connection members 651” and [0150] “Connection members 650”) .
The external contacts on both top and bottom side surfaces as taught by O1 is incorporated as external contacts on both top and bottom side surfaces of T1, K1 (see K1 Fig. 15i external contact elements 612,610 on the bottom which are combined to also be on the top).
The external contacts on both sides as taught by O1 is incorporated as external contacts on both sides of T1,K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of O1 with T1,K1 because the combination allows for electrical connection through both bottom and top side surfaces (see O1 Fig. 9); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known side for external contacts for another in a similar stacked chip device for which the configurations are provided as alternatively selectable to obtain predictable results (see O1 Figs. 6, 8-9).
15. Regarding Claim 13, T1,K1,O1 disclose the method of claim 8, wherein the external contacts comprise solder balls or metal pillars (see O1 Fig. 9 solder bump elements 651, 650).
16. Claim 9 is rejected under 35 U.S.C. 103 as obvious over Thacker et al. (US 2013/0320567 A1), hereinafter as T1, in view of Kim et al. (US 2013/0069239 A1), hereinafter as K1, in view of Oh (US 2009/0321954 A1), hereinafter as O1, in view of Noma et al. (US 2008/0093708 A1), hereinafter as N1
17. Regarding Claim 9, T1,K1,O1 disclose the method of claim 8, wherein singulating the first chip comprises cutting through the first wafer to form angled sidewalls on the first chip (see T1 Fig. 4 and [0051] “dicing vertically with a dicing blade having two angled edges and mechanically grinding and polishing the sides of the substrate to achieve the desired angle”)
T1,K1,O1 do not explicitly disclose etching.
N1 discloses etching (see Figs. 1-5A and [0043] “portions of the first wirings 3 are exposed by etching the second insulation film 6 and the first insulation film 2 using the photoresist film (not shown) as a mask”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of N1 with T1 because the combination allows for reduced cracks and separation in the semiconductor device and allows for a desired shape groove to be formed at a scribing line (see [0037, 0047]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming a cut at a scribing line for another in a similar device to obtain predictable results (see N1 Figs. 1-5A and [0038]).
18. Claim 11 is rejected under 35 U.S.C. 103 as obvious over Thacker et al. (US 2013/0320567 A1), hereinafter as T1, in view of Kim et al. (US 2013/0069239 A1), hereinafter as K1, in view of Oh (US 2009/0321954 A1), hereinafter as O1, in view of Do et al. (US 2013/0214385 A1), hereinafter as D1
19. Regarding Claim 11, T1,K1,O1 disclose the method of claim 8.
T1,K1,O1 do not explicitly disclose wherein forming the through vias comprises: etching openings through the first semiconductor substrate; and filling the openings with a conductive material.
D1 discloses wherein forming the through vias comprises: etching openings through the first semiconductor substrate; and filling the openings with a conductive material (see Figs. 7A-B, 16A-17B and [0072] “via holes can be formed in various processes, including a laser via drilling process or an etching process” and [0074] “A via hole metal deposition process is performed to assembly 900 to deposit conductive material into each of via holes 702”).
The specific method of forming the vias as taught by D1 is incorporated as specific methods of forming the vias of T1,K1,O1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of D1 with T1,K1,O1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming vias for another in a similar device for which alternatively selectable methods are provided to obtain predictable results (see D1 [0072]).
20. Claims 14 and 20 are rejected under 35 U.S.C. 103 as obvious over Thacker et al. (US 2013/0320567 A1), hereinafter as T1, in view of Haba et al. (US 2009/0160065 A1), hereinafter as H1
21. Regarding Claim 14, T1 disclose a method (see Figs. 1-8B) comprising:
singulating a first chip (first one of the elements “CHIP”) from a first wafer (see Fig. 1 and [0033] “chips on a wafer”);
bonding the singulated first chip to a second chip (see Fig. 4, 8A-B second element “CHIP” on which the first chip is stacked, see [0050] “First, layer 1 and layer 2 wafers, each with pits/trenches etched along the dicing lanes, may be stacked using the process shown in FIG. 4”) of a second wafer (see [0050]);
T1 does not explicitly disclose encapsulating the first chip on the second wafer with a dielectric material; forming a redistribution layer over the encapsulated first chip and the second wafer, wherein the redistribution layer is electrically coupled to both the first chip and the second chip; and forming external contacts on the redistribution layer.
H1 discloses (see Figs. 13-17) encapsulating the first chip (element 312 of element 310A, see [0050] “microelectronic elements 312 (e.g., known good die)”) on the second wafer (element 310, see [0051] “wafer 310”) with a dielectric material (element 116 surrounding element 312 of element 310A, see [0051] “dielectric layer 116”); forming a redistribution layer (see Fig. 17 and [0055] “a redistribution layer including additional traces 326 can be provided which extends between the pads at edge 342 and outwardly beyond a third edge 344 of the microelectronic element 312”) over the encapsulated first chip and the second wafer (see Figs. 16-17, [0055]), wherein the redistribution layer is electrically coupled to both the first chip and the second chip (see Figs. 16-17, [0055]); and forming external contacts on the redistribution layer (element 366, and see Fig. 9 elements 74, see [0042] “Pads or solder bumps 74 may be formed to be in contact with end lead portion 75 as shown.”).
The encapsulation and external electrical connection as taught by H1 is incorporated as encapsulation and external electrical connection of T1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with T1 because the combination allows for improved tolerance for forming leads for stacked chip electrical communication with each other and external elements (see H1 [0054-0055]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known stacked die packaging for another in a similar device to obtain predictable results (see H1 [0054-0055]; also see T1 Figs. 3-6 elements 122, see [0055] “TSVs 122 … other TSVs and planar redistribution layers on surfaces 112 and/or sides 114 may be designed and fabricated as needed for distribution of signal, power and ground”).
22. Regarding Claim 20, T1, H1 disclose the method of claim 14, wherein bonding the singulated first chip comprises forming direct bonds between the first chip and the second chip (see T1 Fig. 4).
23. Claims 15 and 18 are rejected under 35 U.S.C. 103 as obvious over Thacker et al. (US 2013/0320567 A1), hereinafter as T1, in view of Haba et al. (US 2009/0160065 A1), hereinafter as H1, in view of Noma et al. (US 2008/0093708 A1), hereinafter as N1
24. Regarding Claim 15, T1, H1 disclose the method of claim 14, wherein singulating the first chip comprises cutting through the first wafer to form angled sidewalls on the first chip (see T1 Fig. 4 and [0051] “dicing vertically with a dicing blade having two angled edges and mechanically grinding and polishing the sides of the substrate to achieve the desired angle”).
T1,H1 do not explicitly disclose etching.
N1 discloses etching (see Figs. 1-5A and [0043] “portions of the first wirings 3 are exposed by etching the second insulation film 6 and the first insulation film 2 using the photoresist film (not shown) as a mask”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of N1 with T1 because the combination allows for reduced cracks and separation in the semiconductor device and allows for a desired shape groove to be formed at a scribing line (see [0037, 0047]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming a cut at a scribing line for another in a similar device to obtain predictable results (see N1 Figs. 1-5A and [0038]).
25. Regarding Claim 18, T1, H1 disclose the method of claim 14, further comprising, after forming the external contacts, singulating the second wafer to separate the second chip with the bonded first chip from other second chips of the second wafer (see H1 Figs. 9-10C and [0045]).
26. Claim 19 is rejected under 35 U.S.C. 103 as obvious over Thacker et al. (US 2013/0320567 A1), hereinafter as T1, in view of Haba et al. (US 2009/0160065 A1), hereinafter as H1, in view of Shenoy et al. (US 2013/0242493 A1), hereinafter as S1
27. Regarding Claim 19, T1, H1 disclose the method of claim 14.
T1, H1 do not explicitly disclose wherein the redistribution layer comprises multiple dielectric layers and multiple conductive layers.
S1 discloses wherein the redistribution layer comprises multiple dielectric layers and multiple conductive layers (see Fig. 13 and [0121] “The routing layer 1316a is a multi-layer redistribution network including alternating layers of metallization and dielectric material”).
The multilayer RDL as taught by S1 is incorporated for the RDL to be multilayer of T1, H1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with T1,H1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known RDL for another in a similar device to obtain predictable results (see S1 Fig. 13)
Allowable Subject Matter
28. Claims 10, 12, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
29. Claim 10, “planarizing the dielectric material and the first semiconductor substrate before forming the through vias” – as instantly claimed and in combination with the additionally claimed limitations.
30. Claim 12, “thinning the first semiconductor substrate after the encapsulating and before forming the through vias” – as instantly claimed and in combination with the additionally claimed limitations.
31. Claim 16, “forming through vias in the first chip after the encapsulating and before forming the redistribution layer” – as instantly claimed and in combination with the additionally claimed limitations.
32. Claim 17, “planarizing the dielectric material and the first chip before forming the redistribution layer” – as instantly claimed and in combination with the additionally claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Primary Examiner, Art Unit 2818
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