DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 112 3
A. Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 3
1. Claims 1, 9, and 15 3
2. Claims 6 and 18 4
III. Claim Rejections - 35 USC § 102 5
A. Claims 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0033727 (“Lee-727”). 6
IV. Claim Rejections - 35 USC § 103 7
A. Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-727. 7
B. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0035902 (“Kang”) in view of Lee-727. 8
C. Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0248404 (“Chiu”) in view of US 2020/0098685 (“Lee-685”) and Lee-727. 13
V. Pertinent Prior Art 19
Conclusion 19
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1. Claims 1, 9, and 15
The invention is, for purposes of the “written description” inquiry, whatever is now claimed. Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991). One shows “possession” by descriptive means such as words, structures, figures, diagrams, and formulas that fully set forth the claimed invention. Lockwood v. American Airlines, Inc., 107 F.3d 1565, 1572 (Fed. Cir. 1997). It is not sufficient for purposes of the written description requirement that the disclosure, when combined with the knowledge in the art, would lead one to speculate as to modifications that the inventor might have envisioned, but failed to disclose. Id.
Each of independent claims 1, 9, and 15 is drafted with broader scope than that for which there is sufficient support in the Instant Application to show the Instant Inventors were in possession at the time of filing of either the provisional or grandparent applications. In this regard, in lines 6-7, claim 1 recites the limitation,
a carbon-based layer … on at least a portion of sidewalls of the second metal structure …
Each of independent claims 9 (lines 5-6) and 15 (lines 5-6) recites the same limitation.
The limitation “at least a portion” allows the carbon-based layer to be formed on the entire sidewall of the second metal layer. However, there is only support in the Instant Application for forming the carbon-based layer on a portion of the sidewall, but not on the entire sidewall, of the second metal layer, as evidenced by at least Figs. 2, 5H, and 7F. Moreover, forming the carbon-based layer on the entire sidewall of the second metal layer would prevent said carbon-based layer from serving an intended function of blocking deposition of the barrier layer on the top surface of the first metal layer, as shown in each of Figs. 5F and 7E and discussed in the Instant Specification.
Claims 2-8, 10-14, and 16-20 are rejected for including the same unsupported limitation by depending from one of claims 1, 9, and 15, either directly or indirectly.
2. Claims 6 and 18
Claims 6 and 18 read,
6. The semiconductor structure of claim 5, wherein the carbon-based layer is at an interface between the first metal structure and the barrier layer.
18. The semiconductor structure of claim 17, wherein the carbon-based layer is at an interface between the first metal structure and the barrier layer.
The Instant Specification fails to provide sufficient support to show that the Instant Inventors were in possession of the limitations of the features in claims 6 and 18. By definition, an interface is the face formed by the contacting surfaces of two materials. Without contact, there is no interface. A primary purpose of including the carbon-based layer 256, 262a is to prevent contact between the barrier layer 406, 606 of the overlying metal structure 240, 246a and the top surface of the underlying metal structure 242, 240a (Figs. 5H and 7G, respectively) in order to reduce the contact resistance (Instant Specification e.g. ¶ 62). Therefore, there is no interface between the first metal structure 240 or 240a and the barrier layer 406 or 606, respectively, specifically because the carbon-based layer 256 or 262a, respectively, blocks the contact, on purpose.
III. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0033727 (“Lee-727”).
With regard to claims 9-12, Lee-727 discloses, generally in Figs. 21-23,
9. A semiconductor structure, comprising:
[1] a first metal structure 80/31 [¶¶ 52, 57-58, 64];
[2] a second metal structure 85/36 [¶ 59] on the first metal structure 80/31 and interfacing with the first metal structure 80/31 at a metal interface; and
[3a] a carbon-based layer 41 [e.g. graphene; ¶¶ 24, 25, 27, 57-58; Fig. 21] on a top surface of the first metal structure 80/31 and on at least a portion of sidewalls of the second metal structure 85/36 [as shown in Fig. 23],
[3b] wherein the carbon-based layer 41 is substantially absent from the metal interface [as shown in Figs. 22-23].
10. The semiconductor structure of claim 9, further comprising: a first barrier layer 21 [¶ 55] between the first metal structure 80/31 and a first oxide layer 10B [¶¶ 17, 12] .
11. The semiconductor structure of claim 9, further comprising: a second barrier layer 61 [¶ 59] between the second metal structure 85/36 and a second oxide layer 50 [¶¶ 29, 12].
12. The semiconductor structure of claim 11, wherein the carbon-based layer 41 is located between the first metal structure 80/31 and the second barrier layer 61 to substantially prevent contact between the first metal structure 80/31 and the second barrier layer 61.
IV. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-727.
Claim 13 reads,
13. The semiconductor structure of claim 9, further comprising:
[1] an etch stop layer adjacent to the carbon-based layer,
[2] wherein the etch stop layer has a depth that is within a range from approximately 1 nanometer (nm) to approximately 3 nm.
The prior art of Lee-727, as explained above, discloses each of the features of claim 9.
With regard to claim 13, Lee-727 further discloses,
13. The semiconductor structure of claim 9, further comprising:
[1] an etch stop layer 45 [¶¶ 28, 59] adjacent to the carbon-based layer 41,
[2] wherein the etch stop layer 45 has a depth that is within a range from approximately …[5]… nanometer (nm) to approximately …[15]… nm [¶ 28].
Lee-727 states that “[t]he thickness of the ESL 45 is in a range from about 5 nm to about 15 nm in some embodiments.” (¶ 28) However, the claimed range of 1 nm to 3 nm is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range of 5 nm to 15 nm. See In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art).
With regard to claim 14, Lee-727 further discloses,
14. The semiconductor structure of claim 9, wherein the carbon-based layer 41 has a depth that is within a range from approximately 1 nanometer (nm) to approximately 5 nm [i.e. 0.3 nm to 2 nm (¶¶ 24, 25, 27, 57-58)].
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
B. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0035902 (“Kang”) in view of Lee-727.
Claim 1 reads,
1. A semiconductor structure, comprising:
[1] a first metal structure adjacent to a first dummy metal structure within a first oxide layer;
[2] a second oxide layer above the first oxide layer;
[3] a second metal structure on the first metal structure and within the second oxide layer; and
[4a] a carbon-based layer on a top surface of the first metal structure and on at least a portion of sidewalls of the second metal structure,
[4b] wherein the carbon-based layer is substantially absent from a metal interface between the first metal structure and the second metal structure.
With regard to claim 1, Kang discloses, generally in Figs. 3A-4C,
1. A semiconductor structure, comprising:
[1] a first metal structure CB [¶ 53] adjacent to a first dummy metal structure DCB [¶ 53] within a first oxide layer IL1 [¶ 52];
[2] a second oxide layer IL2 [¶ 54] above the first oxide layer IL1;
[3] a second metal structure VB or VB/M1 [¶ 54] on the first metal structure CB and within the second oxide layer IL2; and
[4a] –[4b] … [not taught] …
With regard to features [4a]-[4b] of claim 1 and claim 2, Kang does not disclose the carbon-based layer or the etch stop layer and does not therefore the limitations of features [4a]-[4b] of claim 1 or claim 1.
As explained above, Lee-727 includes a graphene layer 40 or 41 both on the top surfaces of metal structures, e.g. 30 in Fig. 13 or 80/31 in Fig. 23, as well as etching through the graphene layer 40 or 41 to allow the overlying metal structure, 60/35 in Fig. 13 or 85/36 in Fig. 23, to contact the respective underlying metal structure 30 or 80/31, wherein the remaining graphene layer 40 or 41 contacts the sidewalls of the overlying metal structure 60/35 or 85/36.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the graphene layer 40 or 41 of Lee-727 on the top surfaces of the metal structures CB of Kang, in order to reduce the line resistivity by reducing surface scattering of electrons, as well as to increase the maximum current density, as explained in Lee-727 (¶ 71), as well as the un-discussed advantages (¶ 72).
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to etch through the graphene layer formed on the first metal structure CB of Kang/Lee-727 to allow direct contact with an overlying metal structure VB of Kang, because Lee-727 teaches that this configuration is suitable for contacts between metal layers.
Finally, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an etch stop layer 45 of Lee-727 between IL1 and IL2 of Kang in order to provide an etch stop during the etching of the opening in IL2 to the underlying metal structure CB of Kang, as taught in Lee-727.
Thus, Kang modified according to Lee-727 teaches,
[4a] a carbon-based layer [40 or 41 of Lee-727] on a top surface of the first metal structure [CB of Kang] and on at least a portion of sidewalls of the second metal structure [VB of Kang],
[4b] wherein the carbon-based layer [40 or 41 of Lee-727] is substantially absent from a metal interface between the first metal structure [CB of Kang] and the second metal structure [VB of Kang] [as shown in Figs. 13 and 23 of Lee-727].
2. The semiconductor structure of claim 1, further comprising:
[1] at least one etch stop layer [45 of Lee-727] between the first oxide layer [IL1 of Kang] and the second oxide layer [IL2 of Kang],
[2] wherein the carbon-based layer [40 or 41 of Lee-727] is at an interface between the first metal structure [CB of Kang] and the at least one etch stop layer [45 of Lee-727] [as shown in Fig. 13 and 23 of Lee-727].
This is all of the limitations of claims 1 and 2.
With regard to claim 3, Kang further discloses,
3. The semiconductor structure of claim 1, further comprising:
[1] a second dummy metal structure DM1 above the first dummy metal structure DCB and within the second oxide layer IL2,
[2] wherein the second dummy metal structure DM1 does not contact the first dummy metal structure DCB.
With regard to claim 4, the embodiment of Kang shown in Figs. 7-8 modified according to Lee-727 as explained under claim 1, above further discloses,
4. The semiconductor structure of claim 1, further comprising:
[1] an additional carbon-based layer [40 or 41 of Lee-727] on a top surface of the first dummy metal structure [DCB1 or DCB2 of Kang (¶ 72)],
[2] wherein the additional carbon-based layer is at an interface between the first dummy metal structure DCB1 or DCB2 and the second oxide layer IL2.
Because the active CB and dummy DCB metal structures are simultaneously made in the same layers with the same materials, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the carbon-based layer of Lee-727 on all of the metallization, thereby including the dummy metal structures, in order to simplify the manufacturing versus having separate lithography and deposition processes for the active metal structures versus the dummy metal structures.
This is all of the limitations of claim 4.
Claims 5 and 6 read,
5. The semiconductor structure of claim 1, further comprising: a barrier layer between the second metal structure and the second oxide layer.
6. The semiconductor structure of claim 5, wherein the carbon-based layer is at an interface between the first metal structure and the barrier layer.
Kang does not disclose the materials from which the metal structures, e.g. CB, DCB, VB, DVB, M1, are made and does not consequently disclose a barrier layer or any feature associated with a barrier layer.
Lee-727 further teaches a barrier layer 60 or 61 between the second metal structure, 35 in Fig. 13 or 85/36 in Fig. 23, respectively (Lee727: ¶¶ 32-33, 59-60) as required by claim 5.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the metal structures of Kang, e.g. CB, VB, M1, DCB, DVB, DM1, from the metal structure materials in Lee-727—thereby including a barrier layer between the second metal structure VB and the second oxide layer IL2—in order to prevent diffusion of metal from the bulk fill portion of VB and the second oxide layer IL2—as is the art known purpose of a barrier layer. In addition, because Kang is merely silent as to their composition such that one having ordinary skill in the art would use known materials for the same intended purpose of forming contacts and interconnect that connects transistors in a semiconductor device, such as the barrier layers and metal materials of Lee-727.
Fig. 13 of Lee-727 shows that the residual graphene layer 40 is literally “at an interface between the first metal structure 30 and the barrier layer 60 on the overlying metal structure 35. Thus, making the metal structures of Kang according to Fig. 13 of Lee-727, as explained as an option under claim 5, would result in the limitations of claim 6 also being taught.
This is all of the limitations of claims 5 and 6.
With regard to claims 7 and 8, Kang further discloses,
7. The semiconductor structure of claim 1, wherein
[1] the first metal structure CB comprises a gate contact [i.e. to gate electrode GE (¶ 53)], a metal source contact, or a metal drain contact, and
[2] the second metal structure VB or VB/M1 comprises an interconnect [¶ 54].
8. The semiconductor structure of claim 1, wherein the first metal structure CB comprises a contact plug [i.e. to gate electrode GE (¶ 53)], and the second metal structure VB or VB/M1 comprises a metallization layer.
C. Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0248404 (“Chiu”) in view of US 2020/0098685 (“Lee-685”) and Lee-727.
Claim 15 reads,
15. A semiconductor structure, comprising:
[1] a first metal structure adjacent to a first dummy metal structure within a first oxide layer;
[2] a second oxide layer above the first oxide layer;
[3] a second metal structure on the first metal structure and within the second oxide layer;
[4a] a carbon-based layer on a top surface of the first metal structure and on at least a portion of sidewalls of the second metal structure,
[4b] wherein the carbon-based layer is substantially absent from an interface between the first metal structure and the second metal structure;
[5] a third oxide layer above the second oxide layer;
[6] a third metal structure on the second metal structure and within the third oxide layer; and
[7a] a second carbon-based layer on a top surface of the second metal structure and on at least a portion of sidewalls of the third metal structure,
[7b] wherein the carbon-based layer is substantially absent from an interface between the second metal structure and the third metal structure.
With regard to claim 15, Chiu discloses, generally in Fig. 1,
15. A semiconductor structure, comprising:
[1] a first metal structure [28A in M1 (¶¶ 13-14)] adjacent to a first dummy metal structure [28B in M1 (¶¶ 13-14)] within a first … [low-k dielectric]… layer [32 in M1] [infra];
[2] a second … [low-k dielectric]… layer [32 in M2] above the first oxide layer [32 in M1] [infra];
[3] a second metal structure [30A/28A in M2] on the first metal structure 60 or 64 and within the second oxide layer [32 in M2];
[4a]-[4b] … [not taught] …
[5] a third oxide layer [32 above M2] above the second oxide layer [32 in M2];
[6] a third metal structure [30A/28A in 32 above M2] on the second metal structure [30A/28A in M2] and within the third oxide layer [32 above M2]; and
[7a]-[7b] … [not taught] …
With regard to features [1], [2], and [5] of claim 15, Chiu states that “[d]ielectric layers 32 in interconnect structure 26 may include low-k dielectric layers, which may have k values lower than about 3.0, or even lower than about 2.5.” (Chiu: ¶ 13), but does not give a material for the low-k dielectric layer 32 and does not therefore disclose that it is an “oxide” as required for each of features [1], [2], and [5].
Lee-685, like Chiu, teaches a semiconductor device including MOSFET transistors with a multilayer metallization having ILDs 44, 46, 48 that can be made of low-k dielectric materials (Lee-685: ¶ 26). Lee-685 further teaches that said low-k dielectric layers 44, 46, 48 can be low-k oxides, stating, “Exemplary low-k dielectric materials include FSG [i.e. fluorosilicate glass], carbon doped silicon oxide” (Lee-685: ¶ 26).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a low-k oxide such as fluorosilicate glass or carbon doped silicon oxide as the low-k dielectric 32 of Chiu because Chiu is merely silent as to the low-k material such that one having ordinary skill in the art would use known materials suitable for the same purpose of making a multilayered metallization in a semiconductor device, such as the low-k oxides taught in Lee-685. As such, the selection of low-k oxides amounts to obvious material choice. (See MPEP 22144.07.)
With regard to features [4a]-[4b] and [7a]-[7b] of claim 15, Chiu does not disclose carbon based layers on the top surfaces of any of the metal structures.
As explained above, Lee-727 includes a graphene layer 40 or 41 both on the top surfaces of metal structures, e.g. 30 in Fig. 13 or 80/31 in Fig. 23, as well as etching through the graphene layer 40 or 41 to allow the overlying metal structure, 60/35 in Fig. 13 or 85/36 in Fig. 23, to contact the respective underlying metal structure 30 or 80/31, wherein the remaining graphene layer 40 or 41 contacts the sidewalls of the overlying metal structure 60/35 or 85/36.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the graphene layer 40 or 41 of Lee-727 on the top surfaces of the metal structures 28A in each of the metal layers M1, M2, etcetera of Chiu, in order to reduce the line resistivity by reducing surface scattering of electrons, as well as to increase the maximum current density, as explained in Lee-727 (¶ 71), as well as the un-discussed advantages (¶ 72).
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to etch through the graphene layer formed on the top surface of each 28A in each metal layer of Chiu/Lee-727 to allow direct contact with each overlying metal structure 30A of 28A/30A of Chiu, because Lee-727 teaches that this configuration is suitable for contacts between metal layers.
Thus, Chiu modified according to Lee-727 teaches features [4a]-[4b] and [7a]-[7b], as follows:
[4a] a carbon-based layer [40 or 41 of Lee-727] on a top surface of the first metal structure [28A in M1 of Chiu] and on at least a portion of sidewalls of the second metal structure [i.e. on each 30A of 30A/28A in M2 of Chiu],
[4b] wherein the carbon-based layer [40 or 41 of Lee-727] is substantially absent from an interface between the first metal structure [28A in M1 of Chiu] and the second metal structure [30A/28A in M2 of Chiu] [as shown in each of Figs. 13 and 23 of Lee-727];
[7a] a second carbon-based layer on a top surface of the second metal structure [28A in M1 of Chiu] and on at least a portion of sidewalls of the third metal structure [i.e. on each 30A of 30A/28A above M2 of Chiu],
[7b] wherein the carbon-based layer [40 or 41 of Lee-727] is substantially absent from an interface between the second metal structure [30A/28A in M2 of Chiu] and the third metal structure [30A/28A above M2 of Chiu] [as shown in each of Figs. 13 and 23 of Lee-727].
This is all of the limitations of claim 15.
Claim 16 reads,
16. The semiconductor structure of claim 15, further comprising:
[1] at least one etch stop layer between the first oxide layer and the second oxide layer,
[2] wherein the carbon-based layer is at an interface between the first metal structure and the at least one etch stop layer.
Chiu does not teach an etch stop layer and does not consequently disclose the features of claim 16.
As explained above, Figs. 13 of Lee-727 further teaches an etch stop layer 45 formed be the first 10 and second 50 dielectric layers and over the graphene layer 40 or 41, wherein “wherein the carbon-based layer 40 or 41 is at an interface between the first metal structure 30 and the at least one etch stop layer 45”. In addition, Lee-685 teaches an etch stop layer 52, 54, 56 between each of the dielectric layers 42, 44, 46, 48.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an etch stop layer 45 of Lee-727 between each of the low-k oxide layers 32 of Chiu/Lee-685, in order to provide an etch stop during the etching of the opening in 32 to the underlying metal structure of Chiu, as taught in Lee-727.
Thus, Chiu modified according to Lee-727 or Lee-727 and Lee-685 further teaches,
16. The semiconductor structure of claim 15, further comprising:
[1] at least one etch stop layer [45 of Lee-727] between the first oxide layer [32 of Chiu/Lee-685 in M1] and the second oxide layer [32 of Chiu/Lee-685 in M2],
[2] wherein the carbon-based layer [40 or 41 of Lee-727] is at an interface between the first metal structure [28A in M1 of Chiu] and the at least one etch stop layer [45 of Lee-727] [as shown in Fig. 13 of Lee-727].
Claims 17-18 reads,
17. The semiconductor structure of claim 15, further comprising: a barrier layer between the second metal structure and the second oxide layer.
18. The semiconductor structure of claim 17, wherein the carbon-based layer is at an interface between the first metal structure and the barrier layer.
Chiu does not disclose barrier layers.
Lee-727 further discloses,
17. The semiconductor structure of claim 15, further comprising: a barrier layer 60 between the second metal structure 35 and the second oxide layer 50 [Lee-727: Fig. 13 (supra)].
18. The semiconductor structure of claim 17, wherein the carbon-based layer 40 is at an interface between the first metal structure 30 and the barrier layer 60.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a barrier layer around the bulk fill in each of the metal structures 28A, 30A/28A in each of the metal layers M1, M2, through M-top in Chiu, in order to prevent diffusion of metal from the bulk fill portion of and the second oxide layer 32 of M2—as is the art known purpose of a barrier layer.
So modified, the carbon-based layer 40 of Lee-727 used on the top surfaces of each metal structure 28A, 30A/28A of Chiu is at an interface between said first metal structure 28A of M1 and the barrier layer 60 of Lee-727 used in Chiu around the second metal structure 30A/28A, as shown in Fig. 13 of Lee-727.
This is all of the limitations of claims 17-18.
With regard to claims 19-20, Chiu further discloses,
19. The semiconductor structure of claim 15, wherein
[1] the first metal structure 28 comprises a gate contact [to the gate electrode of the transistor 24 as shown in Fig. 1 of Chiu (Chiu: ¶ 13: “Active circuits 24 may include complementary metal-oxide-semiconductor (CMOS) transistors …”)], a metal source contact, or a metal drain contact, and
[2] the second metal structure [30A/28A in M2] comprises an interconnect [as shown in Fig. 1 of Chiu].
20. The semiconductor structure of claim 15, wherein
[1] the first metal structure [28A of M1] comprises a contact plug [as shown in Fig. 1 including plug to the gate electrode of the transistor 24], and
[2] the second metal structure [30A/28A in M2] comprises a metallization layer [as shown in Fig. 1].
V. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2014/0291819 (“Barth”) is cited for disclosing each of the limitations of at least claim 9. See Fig. 10 and associated text, noting that layer 222 is graphene (¶¶ 43, 88, 89).
US 2014/0284802 (“Sakata”) is cited for disclosing each of the limitations of at least claim 9. See e.g. Figs. 11A-11B and associated text, noting that layer 19 is graphene (¶ 27).
US 2021/0082832 (“Yang”) is cited for disclosing each of the limitations of at least claim 9. See Fig. 3E and associated text, noting that layer 220 is graphene (¶ 22-23).
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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