Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-7, 14, 15, 17, 19, 20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Sills et al, US 20180197862.
Regarding claim 1, Sills discloses : A semiconductor device, comprising: a first dielectric layer(Fig. 36, #18); a first conductive feature in the first dielectric layer(#16); a second dielectric layer over the first dielectric layer(#21); a ferroelectric random-access memory (FeRAM) cell in the second dielectric layer(#62 in #21), wherein the FeRAM cell comprises: a bottom electrode on the first conductive feature(#44 on #16), the bottom electrode extending along an upper surface of the first conductive feature and along sidewalls of the second dielectric layer(#44 on upper surface of #16 and sidewall of #21); a ferroelectric material layer over the bottom electrode(#58 may include ferroelectric materials [0058]), the ferroelectric material layer contacting the sidewalls of the second dielectric layer(#58 contacting sidewalls of #21), wherein the ferroelectric material layer completely covers an upper surface of the bottom electrode(#58 covers upper surface of #45); and a top electrode on the ferroelectric material layer(#60); a third dielectric layer over the second dielectric layer(#22); and a second conductive feature in the third dielectric layer(#75 in #22), the second conductive feature being electrically coupled to the top electrode(#75 electrically coupled to #60 [0099]).
Regarding claim 4, Sills discloses: The semiconductor device of claim 1, wherein the top electrode is surrounded by the ferroelectric material layer in a plan view(Fig. 16, #58 surrounds #60).
Regarding claim 5, Sills discloses : The semiconductor device of claim 1, wherein the bottom electrode has a thickness in a range of 5 nm to 20 nm(#44 may be 30-50 Angstoms [0057]).
Regarding claim 6, Sills discloses : The semiconductor device of claim 1, wherein the ferroelectric material layer has a thickness in a range of 5 nm to 20 nm(#58 may be 30 to 100 Angstroms [0058]).
Regarding claim 7, Sills discloses : The semiconductor device of claim 1, wherein the top electrode has a thickness in a range of 5 nm to 20 nm(Fig. 9, #44 may be 30-50 Angstoms [0057] and #58 may be 30 to 100 Angstroms [0058] and capacitor opening #42 may be 300-600 Angstroms with #60 filling the remainder of capacitor opening [0059]).
Regarding claim 14, Sills discloses : A semiconductor device, comprising: a first conductive feature(Fig. 36, #16); a first dielectric layer over the first conductive feature(#21); a memory cell on the first conductive feature(#62), wherein the memory cell comprises: a bottom electrode in contact with the first conductive feature and the first dielectric layer(#44 contacting #21 and #16); an insulating layer on the bottom electrode(#58), wherein the insulating layer is in contact with a top surface of the bottom electrode and the first dielectric layer(#58 contacting top surface of #44 and #21); and a top electrode on the insulating layer(#60), wherein the top electrode completely fills in a space between inner sidewalls of the insulating layer(#60 fills #42 [0059]); and a second conductive feature on the top electrode(#75).
Regarding claim 15, Sills discloses : The semiconductor device of claim 14, wherein the bottom electrode is U-shaped(Fig. 36, #44 shown to be U-shaped).
Regarding claim 17, Sills discloses : The semiconductor device of claim 14, wherein the insulating layer comprises a first portion below the top surface of the bottom electrode and a second portion above the top surface of the bottom electrode(Fig. 36, #58 is u-shaped and has portions above and below a top surface of #44).
Regarding claim 19, Sills discloses : The semiconductor device of claim 14, wherein the second conductive feature is separated from the bottom electrode by the insulating layer and the top electrode(Fig. 36, #58 completely covers upper surface of #44).
Regarding claim 20, Sills discloses : The semiconductor device of claim 14, wherein the insulating layer comprises hafnium(#58 may comprise hafnium [0058]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 8-13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sills et al, US 20180197862 in view of Chavan et al, US 20190189357.
Regarding claim 2, Sills discloses : The semiconductor device of claim 1.
Sills does not disclose : wherein an upper surface of the top electrode is level with an upper surface of the ferroelectric material layer.
However, in the same field of endeavor, Chavan teaches : wherein an upper surface of the top electrode is level with an upper surface of the ferroelectric material layer(Fig. 5, planarization of #32 and #30 via chemical-mechanical polishing [0044]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the planarization technique of Sills for Chavan to obtain a co-planar upper surface of the ferroelectric material and upper electrode for the overlying conductive material and to remove electrode and ferroelectric material so that an overlying conductive feature can be reliably contacted because they are known equivalents and it would have yielded the predictable result. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 3, Sills as modified by Chavan discloses : The semiconductor device of claim 2.
Chavan teaches : wherein an upper surface of the ferroelectric material layer physically contacts the second conductive feature(Fig. 18, #30 contacting #46).
Regarding claim 8, Sills discloses : A semiconductor device, comprising: a first conductive feature(Fig. 36, #16); a ferroelectric random-access memory (FeRAM) cell on the first conductive feature(#62), wherein the FeRAM cell comprises: a bottom electrode in contact with the first conductive feature(#44 contacting #16), wherein the bottom electrode is U-shaped(#44 is u-shaped); a ferroelectric material layer on the bottom electrode(#58 [0058]), wherein the ferroelectric material layer covers inner sidewalls and a top surface of the bottom electrode(#58 covers sidewalls and top surface of #44); and a top electrode on the ferroelectric material layer(#60).
Sills does not disclose : wherein a top surface of the top electrode is level with a top surface of the ferroelectric material layer; and a second conductive feature on the top electrode.
However, in the same field of endeavor, Chavan teaches : wherein a top surface of the top electrode is level with a top surface of the ferroelectric material layer(Fig. 5, planarization of #32 and 30 via chemical-mechanical polishing [0044]); and a second conductive feature on the top electrode(#46 on top of #32).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the planarization technique of Sills for Chavan to obtain a co-planar upper surface of the ferroelectric material and upper electrode for the overlying conductive material and to remove electrode and ferroelectric material so that an overlying conductive feature can be reliably contacted because they are known equivalents and it would have yielded the predictable result. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 9, Sills as modified by Chavan discloses : The semiconductor device of claim 8.
Sills teaches : further comprising a dielectric layer covering outer sidewalls of the bottom electrode(Fig. 36, #21 covering #44), wherein the ferroelectric material layer is in contact with the dielectric layer(#58 contacting #21).
Regarding claim 10, Sills as modified by Chavan discloses : The semiconductor device of claim 8.
Chavan teaches : wherein the ferroelectric material layer is in contact with the second conductive feature(Fig. 16, #32 contacting #46).
Regarding claim 11, Sills as modified by Chavan discloses : The semiconductor device of claim 8.
Sills teaches : wherein the ferroelectric material layer comprises hafnium oxide(#58 may be comprised of hafnium oxide [0058]).
Regarding claim 12, Sills as modified by Chavan discloses : The semiconductor device of claim 8
Sills teaches : wherein the top electrode is encircled by the ferroelectric material layer in a top-down view(Fig. 16, #58 surrounds #60).
Regarding claim 13, Sills as modified by Chavan discloses : The semiconductor device of claim 8.
Sills teaches in another embodiment : wherein the first conductive feature is a gate electrode of a transistor(Fig. 39, #75l below lower electrode #44).
Regarding claim 16, Sills discloses : The semiconductor device of claim 14.
Sills does not disclose : wherein a top surface of the top electrode is level with a top surface of the insulating layer.
However, in the same field of endeavor, Chavan teaches : wherein a top surface of the top electrode is level with a top surface of the insulating layer(Fig. 5, planarization of #32 and 30 via chemical-mechanical polishing [0044]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the planarization technique of Sills for Chavan to obtain a co-planar upper surface of the ferroelectric material and upper electrode for the overlying conductive material and to remove electrode and ferroelectric material so that an overlying conductive feature can be reliably contacted because they are known equivalents and it would have yielded the predictable result. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sills et al, US 20180197862 in view of Kobayashi, US 20220020757.
Regarding claim 18 Sills discloses : The semiconductor device of claim 14.
Sills does not disclose : further comprising a second dielectric layer on the first dielectric layer, wherein the second conductive feature extends through the second dielectric layer, and wherein the second dielectric layer is in contact with the insulating layer and the top electrode.
However, in the same field of endeavor, Kobayashi teaches : further comprising a second dielectric layer on the first dielectric layer(Fig. 8, #50 on #30), wherein the second conductive feature extends through the second dielectric layer(#51b3 extending through #50), and wherein the second dielectric layer is in contact with the insulating layer and the top electrode(#50 contacting #42b and #41b).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Kobayashi to Sills to have a second dielectric layer in contact with an upper electrode and insulating layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20200395460 – Ferroelectric capacitor.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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