DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,855,012 discloses in claims 1-15. Although the claims at issue are not identical, they are not patentably distinct from each other because regarding claim 1, a method of making a semiconductor device, comprising: providing a substrate comprising a plurality of regions; forming a metal-oxide-semiconductor device extending into the substrate; and forming a plurality of contact pads exposed on a surface of the substrate, wherein each of the plurality of contact pads corresponds to one of the plurality of regions, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad.
Regarding claims 2-5, U.S. Patent No. 11,855,012 discloses in claim 2-8, a method wherein each of the plurality of contact pads has an area smaller than 4 square micrometers; wherein each of the plurality of regions has a ring shape and each of the plurality of contact pads has a shape covering a portion of the ring shape of the corresponding region; wherein a distance from the first contact pad to the second contact pad is between 0.01 micrometer and 5 micrometers; wherein a distance from the second contact pad to the third contact pad is between 0.01 micrometer and 200 micrometers.
Regarding claim 6, U.S. Patent No. 11,855,012 discloses in claim 9, a method of making a semiconductor device, comprising: providing a substrate comprising a plurality of regions each having a ring shape; forming a metal-oxide-semiconductor device extending into the substrate; and forming a plurality of contact pads on a surface of the substrate, wherein each of the plurality of contact pads corresponds to one of the plurality of regions, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad.
Regarding claims 7-13, U.S. Patent No. 11,855,012 discloses in claims 7-13,
a method wherein each of the plurality of contact pads has an area smaller than 4 square micrometers; wherein each of the plurality of regions has a ring shape and each of the plurality of contact pads has a shape covering a portion of the ring shape of the corresponding region; wherein a distance from the first contact pad to the second contact pad is larger than 0.01 micrometer; wherein a distance from the first contact pad to the second contact pad is smaller than 5 micrometers; wherein a distance from the second contact pad to the third contact pad is larger than 0.01 micrometer; wherein a distance from the second contact pad to the third contact pad is smaller than 200 micrometers; wherein the semiconductor device serves as an antenna switch.
Regarding claim 14, U.S. Patent No. 11,855,012 discloses in claim 9, a method of making a semiconductor device, comprising: providing a substrate comprising a plurality of regions, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad; forming a metal-oxide-semiconductor device extending into the substrate; and forming at least one isolation feature extending into the substrate and disposed adjacent to the metal-oxide-semiconductor device.
Regarding claims 15-20, U.S. Patent No. 11,855,012 discloses in claims 10-15,
a method further comprising forming at least four metal layers on the metal-oxide-semiconductor device in a chip portion of the semiconductor device; wherein a quantity of the at least four metal layers is between four and twenty; wherein an insertion loss of the semiconductor device is smaller as a quantity of the at least four metal layers becomes larger; wherein eight metal layers in total are formed on the metal-oxide-semiconductor device in the chip portion of the semiconductor device; further comprising forming at least one metal layer in a packaging portion of the semiconductor device; wherein an insertion loss of the semiconductor device is smaller as a quantity of the at least one metal layer becomes larger.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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