DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 07/31/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 07/31/2024. These drawings are review and accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,125,551 B2 (‘551). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘551 claims.
US Patent No. 12,125,551 B2
US Patent Application No. 2024/0395290 A1
1. A memory device, comprising: a plurality of sense amplifiers; a plurality of memory cells coupled to a plurality of first inputs of the plurality of sense amplifiers respectively; a plurality of data lines coupled to a plurality of second inputs of the plurality of sense amplifiers respectively; a plurality of reference cells arranged in a plurality of columns respectively and coupled to the plurality of data lines respectively, wherein the plurality of reference cells comprises a plurality of resistive elements, wherein a first number of the resistive elements that have a first resistance and are ones, in the plurality of columns, closest to the plurality of sense amplifiers is different from a second number of the resistive elements that have a second resistance and are ones, in the plurality of columns, closest to the plurality of sense amplifiers, the first and second resistances being different from each other; and a connection line coupled to the plurality of data lines, wherein in a read mode, one of the plurality of sense amplifiers is configured to access the plurality of resistive elements arranged in one of the plurality of columns.
2. The memory device of claim 1, wherein in the read mode, the one of the plurality of sense amplifiers is configured to access the plurality of resistive elements arranged in all of the plurality of columns.
3. The memory device of claim 1, wherein the first resistance corresponds to a first logic value of the plurality of memory cells, and the second resistance corresponds to a second logic value of the plurality of memory cells.
4. The memory device of claim 1, wherein first reference cell and the first sense amplifier are arranged in a first column of the plurality of columns.
5. The memory device of claim 4, wherein a second sense amplifier in the plurality of sense amplifiers is coupled to a pinned layer of a third resistive element in the plurality of resistive elements and a read current from the second sense amplifier to a ground terminal flows through the pinned layer of the third resistive element, a free layer of the third resistive element, a free layer of a fourth resistive element in the plurality of resistive elements and a pinned layer of the fourth resistive element sequentially.
6. The memory device of claim 5, wherein the second sense amplifier and the third to fourth resistive elements are arranged in a same column of the plurality of columns.
7. The memory device of claim 1, wherein one of the plurality of sense amplifiers is coupled to a free layer of one of the plurality of resistive elements, the one of the plurality of resistive elements having the low resistance.
8. The memory device of claim 1, wherein one of the plurality of sense amplifiers is coupled to a pinned layer of one of the plurality of resistive elements, the one of the plurality of resistive elements having the high resistance.
9. A memory device, comprising: a first sense amplifier arranged in a first column; a first reference cell comprising a first string of resistive elements of low and high resistances that are in the first column and are coupled between a ground and a first input of the first sense amplifier; a second sense amplifier arranged in a second column and coupled to the first sense amplifier in parallel; and a second reference cell comprising a second string of resistive elements of the low and high resistances that are in the second column and are coupled between the ground and a first input of the second sense amplifier, wherein a first number of resistive elements in the first string of resistive elements is different from a second number of resistive elements in the second string of resistive elements.
10. The memory device of claim 9, further comprising: a third sense amplifier coupled to the second sense amplifier in parallel; and a third reference cell arranged in a third column, coupled to the third sense amplifier, and comprising the first number of the plurality of resistive elements, wherein the plurality of resistive elements in the third reference cell comprise a plurality of fifth resistive elements having the high resistance.
11. The memory device of claim 10, further comprising: a fourth sense amplifier coupled to the third sense amplifier in parallel; and a fourth reference cell arranged in a fourth column, coupled to the fourth sense amplifier, and comprising the first number of the plurality of resistive elements, wherein the plurality of resistive elements in the fourth reference cell comprise a plurality of sixth resistive elements having the low resistance.
12. The memory device of claim 11, wherein in a read mode, one of the first sense amplifier, the second sense amplifier, the third sense amplifier, and the fourth sense amplifier is configured to access all of the plurality of resistive elements in the first reference cell, the second reference cell, the third reference cell, and the fourth reference cell.
13. The memory device of claim 9, wherein the first sense amplifier is coupled to a free layer of one resistive element in the first string of resistive elements, the one of the first string of resistive elements having the low resistance.
14. The memory device of claim 9, further comprising: a plurality of resistive elements arranged in rows and columns including the first and second strings of the resistive elements in the first and second columns, wherein a total resistance value of the resistive elements in a first row of the rows is different from a total resistance value of the resistive elements in a second row, different from the first row, of the rows.
15. A memory device, comprising: a plurality of first sense amplifiers arranged in a plurality of first columns respectively; a plurality of first reference cells arranged in the plurality of first columns respectively, wherein each of the first reference cells comprises a first resistive element and a second resistive element, wherein a corresponding one of the plurality of first sense amplifiers is coupled to a pinned layer of the first resistive element, wherein a free layer of the first resistive element is coupled to a free layer of the second resistive element, and a pinned layer of the second resistive element is coupled to a source line; at least one second sense amplifier arranged in at least one second column; and at least one second reference cell arranged in the at least one second column, wherein the at least one second reference cell comprises a third resistive element and a fourth resistive element, wherein the at least one second sense amplifier is coupled to a free layer of the third resistive element, and a pinned layer of the third resistive element is coupled to a free layer of the fourth resistive element, wherein in a read mode, the second sense amplifier is configured to access a plurality of resistive elements in each of the plurality of first reference cells, wherein a first one of the plurality of first reference cells comprises a first string of resistive elements of low and high resistances that are in a first one of the plurality of first columns and are coupled between a ground and a first input of a first one of the plurality of first sense amplifiers, and a second one of the plurality of first reference cells comprises a second string of resistive elements of the low and high resistances that are in a second one of the plurality of first columns and are coupled between the ground and a first input of a second one of the plurality of first sense amplifiers, wherein a first number of resistive elements in the first string of the resistive elements is different from a second number of resistive elements in the second string of the resistive elements.
16. The memory device of claim 15, wherein in the read mode, the at least one second sense amplifier is further configured to access the at least one second reference cell.
17. The memory device of claim 15, further comprising: a plurality of first reference data lines coupled between the plurality of first sense amplifiers and the plurality of first reference cells respectively, wherein the pinned layer of the first resistive element is directly coupled to a corresponding first reference data line of the first reference data lines.
18. The memory device of claim 17, further comprising: at least one second reference data line coupled between the at least one second sense amplifier and the at least one second reference cell, wherein the free layer of the third resistive element is directly coupled to the at least one second reference data line.
19. The memory device of claim 15, wherein the first resistive element has the high resistance and the second resistive element has the low resistance.
20. The memory device of claim 19, wherein the third resistive element has the low resistance.
1. A memory device, comprising: a plurality of sense amplifiers; and a plurality of reference cells comprising: a plurality of resistive elements arranged in rows and columns, wherein a first row of the resistive elements includes a first number of first resistive elements having a first resistance value and a second number of second resistive elements having a second resistance value different from the first resistance value, wherein the first row is one of the rows that is closest to the plurality of sense amplifier, wherein the first number is different from the second number.
2. The memory device of claim 1, wherein in a read mode, one of the plurality of sense amplifiers is configured to access the plurality of resistive elements arranged in all of the columns.
3. The memory device of claim 1, wherein the first resistance value corresponds to a first logic value of the plurality of reference cells, and the second resistance value corresponds to a second logic value of the plurality of reference cells.
4. The memory device of claim 1, wherein each of the plurality of sense amplifiers are arranged in a corresponding column of the columns of the plurality of resistive elements.
5. The memory device of claim 1, wherein a first sense amplifier in the plurality of sense amplifiers is coupled to a pinned layer of a third resistive element in the plurality of resistive elements and a read current from the first sense amplifier to a ground terminal flows through the pinned layer of the third resistive element, a free layer of the third resistive element, a free layer of a fourth resistive element in the plurality of resistive elements and a pinned layer of the fourth resistive element sequentially.
6. The memory device of claim 5, wherein the first sense amplifier and the third to fourth resistive elements are arranged in a same column of the columns of the plurality of resistive elements.
7. The memory device of claim 1, wherein one of the plurality of sense amplifiers is coupled to a free layer of one of the plurality of resistive elements, the one of the plurality of resistive elements having the first resistance, wherein the first resistance is lower than the second resistance.
8. The memory device of claim 1, wherein one of the plurality of sense amplifiers is coupled to a pinned layer of one of the plurality of resistive elements, the one of the plurality of resistive elements having the second resistance, wherein the first resistance is lower than the second resistance.
9. A memory device, comprising: a first sense amplifier and a second sense amplifier that are coupled to a connection line; a first string of resistive elements that are coupled one after another between the connection line and a ground, wherein the first string is aligned with the first sense amplifier along a first direction; and a second string of resistive elements that are coupled one after another between the connection line and the ground, wherein the second string is aligned with the second sense amplifier along the first direction, wherein a first number of resistive elements in the first string is different from a second number of resistive elements in the second string.
10. The memory device of claim 9, further comprising: a third sense amplifier coupled to the second sense amplifier in parallel; and a third string of resistive elements coupled between the connection line and the ground, wherein the third string is aligned with the third sense amplifier along the first direction, wherein a third number of resistive elements in the third string is equal to the first number of resistive elements in the first string.
11. The memory device of claim 10, further comprising: a fourth sense amplifier coupled to the third sense amplifier in parallel; and a fourth string of resistive elements coupled between the connection line and the ground, wherein the fourth string is aligned with the fourth sense amplifier along the first direction, wherein a fourth number of resistive elements in the fourth string is equal to the first number of resistive elements in the first string, wherein the resistive elements in the fourth string have a high resistance.
12. The memory device of claim 11, wherein in a read mode, one of the first sense amplifier, the second sense amplifier, the third sense amplifier, and the fourth sense amplifier is configured to access all of the first to fourth strings of resistive elements.
13. The memory device of claim 9, wherein the first sense amplifier is coupled to a free layer of one resistive element in the first string of resistive elements, the one of the first string of resistive elements having a low resistance, wherein the memory device further comprises a third sense amplifier coupled to a pinned layer of one resistive element in a third string of resistive elements, the one of the third string of resistive elements having a high resistance.
14. The memory device of claim 9, further comprising: a plurality of resistive elements arranged in rows and columns including the first and second strings of the resistive elements in the first and second columns, wherein a total resistance value of the resistive elements in a first row of the rows is different from a total resistance value of the resistive elements in a second row, different from the first row, of the rows.
15. A memory device, comprising: a plurality of sense amplifiers that are coupled to a connection line and arranged along a first direction; and a row of reference cells along the first direction comprising: a plurality of first reference cells, wherein each of the first reference cells has a first resistive element and is coupled to the connection line through a free layer of the first resistive element; and a plurality of second reference cells, wherein each of the second reference cells has a second resistive element and is coupled to the connection line through a pin layer of the second resistive element, wherein a number of the first reference cells is different from a number of the second reference cells.
16. The memory device of claim 15, wherein in a read mode, one of the plurality of sense amplifiers are configured to access each reference cell of the row of reference cells.
17. The memory device of claim 15, wherein each of the first reference cells further has a third resistive element, wherein a free layer of the first resistive element is coupled to a free layer of the third resistive element.
18. The memory device of claim 17, wherein each of the second reference cells further has a fourth resistive element, wherein a pinned layer of the second resistive element is coupled to a free layer of the fourth resistive element.
19. The memory device of claim 15, wherein the first resistive clement has a high resistance and the second resistive clement has a low resistance.
20. The memory device of claim 19, wherein the third resistive clement has the low resistance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Chih et al (US 9,165,629 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Chih, for example in Figs. 1-5, discloses a memory device (see for example in Figs. 1-2 related in Figs. 3-5), comprising: a plurality of sense amplifiers (e.g., sense amplifiers SA; in Fig. 2B related in Figs. 1, 3-5); and a plurality of reference cells (e.g., 230a and 230b; in Fig. 2B related in Figs. 1, 3-5) comprising: a plurality of resistive elements arranged in rows and columns (e.g., RH and RL; in Fig. 2B related in Figs. 1, 3-5), wherein a first row of the resistive elements includes a first number of first resistive elements having a first resistance value (e.g., RH; in Fig. 2B related in Figs. 1, 3-5) and a second number of second resistive elements having a second resistance value different from the first resistance value (e.g., RL; in Fig. 2B related in Figs. 1, 3-5), wherein the first row is one of the rows that is closest to the plurality of sense amplifier (see for example in Fig. 2B related in Figs. 1, 3-5), wherein the first number is different from the second number (see for example in Fig. 2B related in Figs. 1, 3-5).
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Regarding claim 2, chih, for example in Figs. 1-5, discloses wherein in a read mode (see for example in Fig. 2B related in Figs. 1, 3-5), one of the plurality of sense amplifiers is configured to access the plurality of resistive elements arranged in all of the columns (see for example in Fig. 2B related in Figs. 1, 3-5).
Regarding claim 3, Chih, for example in Figs. 1-5, discloses wherein the first resistance value corresponds to a first logic value of the plurality of reference cells, and the second resistance value corresponds to a second logic value of the plurality of reference cells (see Col. 1, lines 36+).
Regarding claim 4, Chih, for example in Figs. 1-5, discloses wherein each of the plurality of sense amplifiers are arranged in a corresponding column of the columns of the plurality of resistive elements (see for example in Figs. 1-5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al (US 9,165,629 B2 hereinafter “Chih”) in view of Maeda et al (US 7,952,916 B2 hereinafter “Maeda”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 5, Chih, for example in Figs. 1-5, discloses the claimed invention as discussed above. However, Chih is silent with regard to wherein the first sense amplifier in the plurality of sense amplifiers is coupled to a pinned layer of a third resistive element in the plurality of resistive elements and a read current from the first sense amplifier to a ground terminal flows through the pinned layer of the third resistive element, a free layer of the third resistive element, a free layer of a fourth resistive element in the plurality of resistive elements and a pinned layer of the fourth resistive element sequentially.
In the same field of endeavor, Maeda, for example in Figs. 1-22, discloses wherein the first sense amplifier in the plurality of sense amplifiers is coupled to a pinned layer of a third resistive element in the plurality of resistive elements (e.g., p; in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22) and a read current from the first sense amplifier to a ground terminal flows through the pinned layer of the third resistive element (see for example in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22), a free layer of the third resistive element, a free layer of a fourth resistive element in the plurality of resistive elements (e.g., f ; in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22) and a pinned layer of the fourth resistive element sequentially (see for example in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Chih such as method and apparatus for MRAM sense reference trimming (see for example in Figs. 1-5 of Chih) by incorporating the teaching of Maeda such as resistance-change memory (see for example in Figs. 1-22 of Maeda). In order to provide a MRAM device with multiple of reference cells and memory cell array (see for example in Figs. 1-22 of Maeda).
Regarding claim 6, the above Chih/Maeda, combination discloses wherein the first sense amplifier and the third to fourth resistive elements are arranged in a same column of the columns of the plurality of resistive elements (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 7, the above Chih/Maeda, combination discloses wherein one of the plurality of sense amplifiers is coupled to a free layer of one of the plurality of resistive elements (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above), the one of the plurality of resistive elements having the first resistance, wherein the first resistance is lower than the second resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 8, the above Chih/Maeda, combination discloses wherein one of the plurality of sense amplifiers is coupled to a pinned layer of one of the plurality of resistive elements, the one of the plurality of resistive elements having the second resistance, wherein the first resistance is lower than the second resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding Independent Claim 9, Chi, for example in Figs. 1-5, discloses a memory device (see for example in Fig. 2B related in Figs. 1, 3-5), comprising: a first sense amplifier and a second sense amplifier that are coupled to a connection line (e.g., sense amplifiers SA; in Fig. 2B related in Figs. 1, 3-5); a first string of resistive elements that are coupled one after another between the connection line (e.g., RL, RH; in Fig. 2B related in Figs. 1, 3-5), wherein the first string is aligned with the first sense amplifier along a first direction (e.g., in column direction; in Fig. 2B related in Figs. 1, 3-5); and a second string of resistive elements that are coupled one after another between the connection line (see for example in Fig. 2B related in Figs. 1, 3-5), wherein the second string is aligned with the second sense amplifier along the first direction (see for example in Fig. 2B related in Figs. 1, 3-5, as discussed above), wherein a first number of resistive elements in the first string (e.g., compensation reference cells; in Fig. 2B related in Figs. 1, 3-5) is different from a second number of resistive elements in the second string (e.g., reference cells stuck bit; in Fig. 2B related in Figs. 1, 3-5).
However, Chih is silent with regard to the resistive element between the connection line and ground.
In the same field of endeavor, Maeda, for example in Figs. 1-22, discloses the resistive element between the connection line and ground (e.g., to ground; in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Chih such as method and apparatus for MRAM sense reference trimming (see for example in Figs. 1-5 of Chih) by incorporating the teaching of Maeda such as resistance-change memory (see for example in Figs. 1-22 of Maeda). In order to provide a MRAM device with multiple of reference cells and memory cell array (see for example in Figs. 1-22 of Maeda).
Regarding claim 10, the above Chih/Maeda, combination discloses further comprising: a third sense amplifier coupled to the second sense amplifier in parallel (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above); and a third string of resistive elements coupled between the connection line and the ground, wherein the third string is aligned with the third sense amplifier along the first direction, (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above) wherein a third number of resistive elements in the third string is equal to the first number of resistive elements in the first string (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 11, the above Chih/Maeda, combination discloses further comprising: a fourth sense amplifier coupled to the third sense amplifier in parallel (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above); and a fourth string of resistive elements coupled between the connection line and the ground (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above), wherein the fourth string is aligned with the fourth sense amplifier along the first direction, wherein a fourth number of resistive elements in the fourth string is equal to the first number of resistive elements in the first string, wherein the resistive elements in the fourth string have a high resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 12, the above Chih/Maeda, combination discloses wherein in a read mode, one of the first sense amplifier, the second sense amplifier, the third sense amplifier, and the fourth sense amplifier is configured to access all of the first to fourth strings of resistive elements (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 13, the above Chih/Maeda, combination discloses wherein the first sense amplifier is coupled to a free layer of one resistive element in the first string of resistive elements, the one of the first string of resistive elements having a low resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above), wherein the memory device further comprises a third sense amplifier coupled to a pinned layer of one resistive element in a third string of resistive elements, the one of the third string of resistive elements having a high resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 14, the above Chih/Maeda, combination discloses further comprising: a plurality of resistive elements arranged in rows and columns including the first and second strings of the resistive elements in the first and second columns (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above), wherein a total resistance value of the resistive elements in a first row of the rows is different from a total resistance value of the resistive elements in a second row, different from the first row, of the rows (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding Independent Claim 15, Chih, for example in Figs. 1-5, discloses a memory device (see for example in Fig. 2B related in Figs. 1, 3-5), comprising: a plurality of sense amplifiers that are coupled to a connection line and arranged along a first direction (e.g., sense amplifiers SAs; in Fig. 2B related in Figs. 1, 3-5); and a row of reference cells along the first direction (see for example in Fig. 2B related in Figs. 1, 3-5) comprising: a plurality of first reference cells (see for example in Fig. 2B related in Figs. 1, 3-5), wherein each of the first reference cells has a first resistive element and is coupled to the connection line (see for example in Fig. 2B related in Figs. 1, 3-5); and a plurality of second reference cells, wherein each of the second reference cells has a second resistive element and is coupled to the connection line (see for example in Fig. 2B related in Figs. 1, 3-5), wherein a number of the first reference cells is different from a number of the second reference cells (see for example in Fig. 2B related in Figs. 1, 3-5, as discussed above).
However, Chih is silent with regard to coupled to through a free layer of the first resistive element; coupled to through a pin layer of the second resistive element.
In the same field of endeavor, Maeda, for example in Figs. 1-22, discloses to coupled to through a free layer of the first resistive element (see for example in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22); coupled to through a pin layer of the second resistive element (see for example in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Chih such as method and apparatus for MRAM sense reference trimming (see for example in Figs. 1-5 of Chih) by incorporating the teaching of Maeda such as resistance-change memory (see for example in Figs. 1-22 of Maeda). In order to provide a MRAM device with multiple of reference cells and memory cell array (see for example in Figs. 1-22 of Maeda).
Regarding claim 16, the above Chih/Maeda, combination discloses wherein in a read mode, one of the plurality of sense amplifiers are configured to access each reference cell of the row of reference cells (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 17, the above Chih/Maeda, combination discloses wherein each of the first reference cells further has a third resistive element, wherein a free layer of the first resistive element is coupled to a free layer of the third resistive element (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 18, the above Chih/Maeda, combination discloses wherein each of the second reference cells further has a fourth resistive element, wherein a pinned layer of the second resistive element is coupled to a free layer of the fourth resistive element (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 19, the above Chih/Maeda, combination discloses wherein the first resistive element has a high resistance and the second resistive element has a low resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Regarding claim 20, the above Chih/Maeda, combination discloses wherein the third resistive element has the low resistance (see for example in Figs. 1-5 of Chih and also see in Figs. 1-2, 5-9 related in Figs. 3-4, 10-22 of Maeda, as discussed above).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 02/07/2026