Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 7/31/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3.The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-3, 7, 10-14, 16-17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wygant et al. (US 2014/0239979) in view of Chen et al. (US 8,501,587). (“Wy” and “Chen”).
5. Regarding claim 1, Wy teaches A testing apparatus [Figures 1-3, a testing apparatus is shown], comprising: a first wafer having a bottom surface [Figures 1-3, a first wafer 101 having a bottom surface is shown]; a second wafer (disposed over the metal layer and) having a top surface [Figures 1-3, a second wafer 120 (120a, 120b) having a top surface is shown; P(0015) teaches a second substrate providing a membrane 120]; and a plurality of through silicon vias (TSVs) extending in a first direction from the bottom surface of the first wafer to the top surface of the second wafer [Figures 1-3, see TSVs 111, 112].
Wy does not explicitly teach a metal layer disposed over the first wafer.
However, Chen teaches a metal layer disposed over the first wafer [Figures 1K-1L, a metal layer 32, 42 over the first wafer 10 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a metal layer providing interconnect between layers.
6. Regarding claim 2, Wy teaches the testing apparatus.
Wy does not explicitly teach wherein the metal layer comprises: a metal structure; and a dielectric surrounding the metal structure.
However, Chen teaches wherein the metal layer comprises: a metal structure; and a dielectric surrounding the metal structure [Figures 1K-1L, a dielectric layer 31 surrounding the metal layer 32, 42 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a dielectric layer surrounding the metal layer which would help protect the interconnection.
7. Regarding claim 3, Wy teaches wherein the plurality of TSVs are separated from the metal structure in a second direction perpendicular to the first direction [Figures 1-3, see TSV’s 111, 112].
8. Regarding claim 7, Wy teaches the testing apparatus.
Wy does not explicitly teach wherein the metal structure is coupled to a plurality of contacts.
However, Chen teaches wherein the metal structure is coupled to a plurality of contacts [Figures 1K-1L, see metal layers 32, 42].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a metal layer providing interconnect between layers.
9. Regarding claim 10, Wy teaches the testing apparatus.
Wy does not explicitly teach wherein the metal structure comprises a plurality of metal structure segments and contacts are coupled to each of the plurality of metal structure segments
However, Chen teaches wherein the metal structure comprises a plurality of metal structure segments and contacts are coupled to each of the plurality of metal structure segments [Figures 1K-1L, see metal layers 32, 42].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a metal layer providing interconnect between layers.
10. Regarding claim 12, Wy teaches wherein each of the plurality of TSVs are a same distance from a nearest one of the plurality of TSVs in a second direction perpendicular to the first direction [Figures 1-3, see TSV’s 111, 112].
5. Regarding claim 13, Wy teaches A testing apparatus [Figures 1-3, a testing apparatus is shown], comprising: a first wafer; a second wafer; and a plurality of through silicon vias (TSVs) extending from the first wafer to the second wafer [Figures 1-3, a first substrate 101, a second wafer 120 (120a, 120b, see P(0015)) and a plurality of TSVs 111, 112].
Wy does not explicitly teach a testing unit interposed between the first wafer and the second wafer.
However, Chen teaches a testing unit interposed between the first wafer and the second wafer
[Figures 1K-1L, a testing unit 32, 42 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a testing unit providing interconnect between layers.
10. Regarding claim 14, Wy teaches the testing apparatus.
Wy does not explicitly teach wherein the testing unit comprising a metal structure within a dielectric.
However, wherein the testing unit comprising a metal structure within a dielectric [Figures 1K-1L, a metal layer 32, 42 is within a dielectric 31 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a dielectric layer surrounding the metal layer which would help protect the interconnection.
10. Regarding claim 16, Wy teaches wherein the plurality of TSVs extends in a first direction from the first wafer to the second wafer through the dielectric of the testing unit, and wherein the plurality of TSVs are separated from the metal structure in a second direction perpendicular to the first direction [Figures 1-3, see TSV’s 111, 112].
5. Regarding claim 17, Wy teaches A method for fabricating a testing apparatus [Figures 1-3, a method is taught], comprising: forming a first wafer having a bottom surface; forming a second wafer (disposed over the metal layer and) having a top surface; and forming a plurality of through silicon vias (TSVs) extending from the bottom surface of the first wafer to the top surface of the second wafer [Figures 1-3, a first wafer 101 having a bottom surface, a second wafer 120 having a top surface and a plurality of TSVs 111, 112 is shown].
Wy does not explicitly teach forming a metal layer disposed over the first wafer.
However, Chen teaches forming a metal layer disposed over the first wafer [Figures 1K-1L, a metal layer 32, 42 disposed over the first wafer 10 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a metal layer providing interconnect between layers.
10. Regarding claim 18, Wy teaches the method.
Wy does not explicitly teach wherein forming the metal layer comprises: forming a metal structure; and forming a dielectric surrounding the metal structure, wherein the metal structure is coupled to first to fourth contacts.
However, Chen teaches wherein forming the metal layer comprises: forming a metal structure; and forming a dielectric surrounding the metal structure, wherein the metal structure is coupled to first to fourth contacts [Figures 1K-1L, a dielectric layer 31 surrounding the metal layer 32, 42 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Wy with Chen. Doing so would allow Wy to comprise a dielectric layer surrounding the metal layer which would help protect the interconnection.
Allowable Subject Matter
10. Claims 4-6, 8-9, 11, 15, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
4. The testing apparatus of claim 2, wherein the first wafer comprises advance process control monitor (APCM) coupled to the metal structure and the second wafer comprises a plurality of pads coupled to the APCM.
5. The testing apparatus of claim 4, wherein the APCM comprises one or more switching devices and a control circuit that is configured to selectively activate the one or more switching devices.
6. The testing apparatus of claim 4, comprising a die portion and a scribe portion abutting with the die portion along the first direction, and wherein the metal structure is located in the die portion and the APCM and the plurality of pads are located in the scribe portion.
8. The testing apparatus of claim 7, wherein a first current is applied at one of the plurality of contacts, a second current is applied at another one of the plurality of contacts, and a voltage is measured across two other contacts of the plurality of contacts.
9. The testing apparatus of claim 2, wherein the metal layer includes a second metal structure, wherein a current is applied through the metal structure and a leakage current is measured in the second metal structure.
11. The testing apparatus of claim 2, further comprising a second metal layer disposed over the metal layer, the second metal layer including a second metal structure disposed over the metal structure, and wherein a capacitance is measured across the metal structure and the second metal structure.
15. The testing apparatus of claim 14, further comprising: an advance process control monitor (APCM) in the first wafer, wherein the testing unit is coupled to the APCM, and wherein the second wafer comprises a plurality of pads coupled to the APCM.
19. The method of claim 18, further comprising: applying a first current at the first contact; applying a second current, equal and opposite to the first current, at the second contact; and measuring a voltage across the third and fourth contacts.
20. The method of claim 17, wherein the first wafer comprises advance process control monitor (APCM) comprising one or more switching devices and a control circuit, the method further comprises: selectively activating the one or more switching devices via the control circuit.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fox et al. (US 2013/0015502), Figures 1-7 teaches a structure comprising a first substrate, an insulating layer, a second substrate, a metal layer, TSV’s similarly arranged to that of the present application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEEL D SHAH whose telephone number is (571)270-3766. The examiner can normally be reached M-F: 9AM-5:30PM.
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/NEEL D SHAH/Primary Examiner, Art Unit 2858
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